JAJSSE7 November 2023 DRV8214
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
STANDARD MODE | |||||
fSCL | SCL Clock frequency | 0 | 100 | kHz | |
tHD,STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated |
4 | µs | ||
tLOW | LOW period of the SCL clock | 4.7 | µs | ||
tHIGH | HIGH period of the SCL clock | 4 | µs | ||
tSU,STA | Setup time for a repeated START condition | 4.7 | µs | ||
tHD,DAT | Data hold time: For I2C bus devices | 0.035 | 3.45 | µs | |
tSU,DAT | Data set-up time | 250 | ns | ||
tR | SDA and SCL rise time | 1000 | ns | ||
tF | SDA and SCL fall time | 300 | ns | ||
tSU,STO | Set-up time for STOP condition | 4 | µs | ||
tBUF | Bus free time between a STOP and START condition | 4.7 | µs | ||
FAST MODE | |||||
fSCL | SCL Clock frequency | 0 | 400 | kHz | |
tHD,STA | Hold time (repeated) START condition. After this period, the first clock pulse is generated | 0.6 | µs | ||
tLOW | LOW period of the SCL clock | 1.3 | µs | ||
tHIGH | HIGH period of the SCL clock | 0.6 | µs | ||
tSU,STA | Setup time for a repeated START condition | 0.6 | µs | ||
tHD,DAT | Data hold time: For I2C bus devices | 0.035 | 0.9 | µs | |
tSU,DAT | Data set-up time | 250 | ns | ||
tR | SDA and SCL rise time | 300 | ns | ||
tF | SDA and SCL fall time | 300 | ns | ||
tSU,STO | Set-up time for STOP condition | 0.6 | µs | ||
tBUF | Bus free time between a STOP and START condition | 1.3 | µs | ||
tSP | Pulse width of spikes to be supressed by input noise filter | 50 | ns |