JAJSM95A May   2023  – December 2023 DRV8845

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Operating Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Motor Configurations
      2. 7.3.2 Stepper Control Logic
      3. 7.3.3 DC Motor Control
      4. 7.3.4 PWM Current Control
      5. 7.3.5 Current Regulation and Decay Mode
      6. 7.3.6 Blanking Time
      7. 7.3.7 Charge Pump
      8. 7.3.8 Logic-Level Pin Diagram
      9. 7.3.9 Protection Circuits
        1. 7.3.9.1 VM Undervoltage Lockout (UVLO)
        2. 7.3.9.2 VCP Undervoltage Lockout (CPUV)
        3. 7.3.9.3 Overcurrent Protection (OCP)
        4. 7.3.9.4 Thermal Shutdown (OTSD)
        5. 7.3.9.5 Fault Condition Summary
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode (nSLEEP = 0)
      2. 7.4.2 Operating Mode (nSLEEP = 1)
      3. 7.4.3 nSLEEP Reset Pulse
      4. 7.4.4 Functional Modes Summary
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Application Schematics
    3. 8.3 Application Curves
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Bulk Capacitance
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.3 DC Motor Control

Control of the DC motors is accomplished by tying the I0x and I1x pins together, creating an equivalent ENABLE function with maximum current defined by the voltage on the corresponding VREF pin. The DC motors can be driven via a PWM signal on this enable signal, or on the corresponding PHASE pin. Motor control includes forward, reverse, and coast. The turth table is shown in Table 7-5 -

Table 7-5 DC Motor truth table

ENABLEx (I0x = I1x)

PHASEx

OUTxA

OUTxB

Description

H

X

Hi-z

Hi-z

Coast

L

L

L

H

Reverse

L

H

H

L

Forward

When H-bridge 3 and 4 are paralleled, PHASE3, I03 and I13 are used to control the combined H-bridge. VREF3 alone controls the current of the combined H-bridge, and the voltage on VREF4 pin is ignored.

As mentioned in Section 7.3.1, H-bridge 3 and H-bridge 4 can be paralleled together to drive a single DC motor with higher current. To enable this, ensure following steps -

  • PHASE4 must be left OPEN at start-up or when the device exits from sleep mode.

  • Leave I04 and I14 OPEN as well. The combined H-bridge is controlled by PHASE3, I03 and I13.

  • Ensure OUT3A is shorted to OUT4A and OUT3B is shorted to OUT4B.

  • Short SENSE3 to SENSE4 pin.

  • VREF3 voltage alone controls the ITRIP of the combined H-bridge. Leave VREF4 OPEN.

  • ITRIPMax = 2 × VREF3 / (3 × RSENSE), where RSENSE is the sense resistor connected from the shorted SENSE pin to ground.

Each H-bridge can deliver up to 1.5 A current. When paralleled, the combined H-bridge 3 and 4 can deliver up to 3 A current.