JAJSQ88E february   2006  – october 2020 SN65LVDS301

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
    2. 6.2  Thermal Information
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Device Electrical Characteristics
    5. 6.5  Output Electrical Characteristics
    6. 6.6  Input Electrical Characteristics
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Characteristics
    9. 6.9  Device Power Dissipation
    10. 6.10 Typical characteristics
  8. 7 Parameter Measurement Information
    1.     19
      1. 7.1.1 Power Consumption Tests
        1. 7.1.1.1 Typical IC Power Consumption Test Pattern
        2. 7.1.1.2 22
      2. 7.1.2 Maximum Power Consumption Test Pattern
      3. 7.1.3 Output Skew Pulse Position & Jitter Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Swap Pin Functionality
      2. 8.3.2 Parity Bit Generation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serialization Modes
        1. 8.4.1.1 1-Channel Mode
        2. 8.4.1.2 2-Channel Mode
        3. 8.4.1.3 3-Channel Mode
      2. 8.4.2 Powerdown Modes
      3. 8.4.3 Shutdown Mode
      4. 8.4.4 Standby Mode
      5. 8.4.5 Active Modes
      6. 8.4.6 Acquire Mode (PLL approaches lock)
      7. 8.4.7 Transmit Mode
      8. 8.4.8 Status Detect and Operating Modes Flow diagram
  10. 9 Application information
    1. 9.1 Application Information
    2. 9.2 Preventing Increased Leakage Currents in Control Inputs
    3. 9.3 VGA Application
    4. 9.4 Dual LCD-Display Application
    5. 9.5 Typical Application Frequencies
      1. 9.5.1 Calculation Example: HVGA Display
  11. 10Power Supply Design Recommendation
    1. 10.1 Decoupling Recommendation
  12. 11Layout
    1. 11.1 Layout Guidelines
  13. 12Device and Documentation Support
    1. 12.1 サポート・リソース
    2. 12.2 Trademarks
    3. 12.3 静電気放電に関する注意事項
    4. 12.4 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.4.4 Standby Mode

The SN65LVDS301 enters the Standby mode if TXEN is high and the PCLK input signal frequency is less than 500kHz. All circuitry except the PCLK input monitor is shut down, and all outputs enter high-impedance mode. The current consumption in Standby mode is very low. When the PCLK input signal is completely stopped, the IDD current consumption is less than 10 μA. The PCLK input must not be left floating.

Note:

A floating (left open) CMOS input allows leakage currents to flow from VDD to GND. To prevent large leakage current, a CMOS gate must be kept at a valid logic level, either VIH or VIL. This can be achieved by applying an external voltage of VIH or VIL to all SN65LVDS301 inputs.