JAJSQ88E february 2006 – october 2020 SN65LVDS301
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
IDD | 1ChM | VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(CLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, alternating 1010 serial bit pattern |
fPCLK = 4 MHz | 9.0 | 11.4 | mA | ||
fPCLK = 6 MHz | 10.6 | 12.6 | ||||||
fPCLK = 15 MHz | 16 | 18.8 | ||||||
VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, typical power test pattern (see Table 7-2) |
fPCLK = 4 MHz | 8.0 | mA | |||||
fPCLK = 6 MHz | 8.9 | |||||||
fPCLK = 15 MHz | 14.0 | |||||||
2ChM | VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(CLK)=RL(Dx)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, alternating 1010 serial bit pattern; |
fPCLK = 8 MHz | 13.7 | 15.9 | mA | |||
fPCLK = 22 MHz | 18.4 | 22.0 | ||||||
fPCLK = 30 MHz | 21.4 | 25.8 | ||||||
VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, typical power test pattern (see Table 7-3) |
fPCLK = 8 MHz | 11.5 | mA | |||||
fPCLK = 22 MHz | 16.0 | |||||||
fPCLK = 30 MHz | 19.1 | |||||||
3ChM | VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, alternating 1010 serial bit pattern |
fPCLK = 20 MHz | 20.0 | 22.5 | mA | |||
fPCLK = 65 MHz | 29.1 | 36.8 | ||||||
VDD
=VDDPLLA=VDDPLLD=VDDLVDS,
RL(PCLK)=RL(D0)=100 Ω,
VIH=VDD, VIL=0 V, TXEN at
VDD, typical power test pattern (see Table 7-4) |
fPCLK = 20 MHz | 15.9 | mA | |||||
fPCLK = 65 MHz | 24.7 | |||||||
Standby Mode | VDD = VDDPLLA = VDDPLLD = VDDLVDS, RL(PCLK)=RL(D0)=100 Ω, VIH=VDD, VIL=0 V, all inputs held static high or static low | 0.61 | 10 | μA | ||||
Shutdown Mode | 0.55 | 10 | μA |