JAJSQ88E february 2006 – october 2020 SN65LVDS301
PRODUCTION DATA
- 1
- 1 特長
- 2 アプリケーション
- 3 概要
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings #GUID-B6F760D2-14EB-4E2D-91AA-4EF9E63722A7/SLLS6819275
- 6.2 Thermal Information
- 6.3 Recommended Operating Conditions
- 6.4 Device Electrical Characteristics
- 6.5 Output Electrical Characteristics
- 6.6 Input Electrical Characteristics
- 6.7 Switching Characteristics
- 6.8 Timing Characteristics
- 6.9 Device Power Dissipation
- 6.10 Typical characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application information
- 10Power Supply Design Recommendation
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
6.10 Typical characteristics
Figure 6-2 Powerdown, Standby Supply Current vs
Temperature
Figure 6-4 Supply Current vs PCLK Frequency
Figure 6-6 PLL Bandwidth
Figure 6-8 Cycle-to-cycle Output Jitter vs
Temperature
Figure 6-10 Data Eye Pattern, 2-channel Mode
Figure 6-12 QVGA Output Waveform
Figure 6-14 VGA 2-channel Output Waveform
Figure 6-16 XGA 3-channel Output Waveform
Figure 6-18 PLL Phase Noise
Figure 6-20 Output Common Mode Noise Rejection
Figure 6-3 Supply Current IDD vs
Temperature
Figure 6-5 Differential Output Swing vs PCLK
Frequency
Figure 6-7 Cycle-to-cycle Output Jitter vs PCLK
Frequency
Figure 6-9 Output Pulse Position vs Temperature
Figure 6-11 Data Eye Pattern, 3-channel Mode
Figure 6-13 VGA 2-channel Output Waveform
Figure 6-15 VGA 3-channel Output Waveform
Figure 6-17 XGA 3-channel Output Waveform on the
SN65LVDS302 when driven by the SN65LVDS301
Figure 6-19 Output Return Loss
Figure 6-21 Crosstalk
Figure 6-22 GTEM SAE J1752/3 EMI Test