The use of FPGAs (Field Programmable Gate Arrays) in electronic systems and products is popular as FPGAs have grown and as the variety of offerings have increased. The popularity of FPGAs has increased given the flexibility that FPGAs afford users in terms of allowing them to reprogram processors rather than waiting for a new silicon spin. In addition, FPGAs reduce design cycle times by enabling system designers to quickly prototype new functionality by implementing firmware updates rather than going through time consuming hardware changes. FPGAs are available in a wide spectrum of capabilities with many of the newest FPGAs rivaling some of the most complex custom ASICs (Application Specific Integrated Circuits) that are being developed.

The increases in FPGA processing power, I/Os (Input/Output), and memory provide designers with many options for implementing specific designs. However, using these FPGA resources often comes at the cost of higher power dissipation when using many of the resources that are available on modern FPGAs. FPGA vendors often provide recommendations for provisioning the vendors FPGAs for achieving a lower overall power envelope for a given FPGA design.

Often, FPGA provisioning recommendations require FPGA core voltages to be lowered to below common voltage rails such as 1.8V or 3.3V. For example, complex FPGAs with large Look Up Table (LUT) counts, FPGA vendors can recommend operating the FPGA at a core voltage such as 1.2V or even lower to achieve designed for power consumption. The lower core voltage translates into lower I/O voltages that the FPGA can support. One of the design challenges that system designers face when working with an FPGA operating at a core voltage of 1.2V or lower is that the peripheral devices the FGPA connects with often operates at I/O voltages much higher than the FPGA I/O can support, which results in an I/O voltage level mismatch (See Figure 1).

For systems designers, increasing the FPGAs, I/O voltage require increasing the core voltage of the entire FPGA or a significant portion to a higher level resulting in higher overall power dissipation. If only a few of the FPGAs I/Os have I/O level mismatches, this increases the overall power envelope of the entire FPGA. One design that enables system designers to maintain the FPGAs lower core voltage and resolve I/O level mismatches is to use simple voltage level translator devices.

Level translation devices provide system designers a simple and cost-effective design for resolving the systems I/O level mismatch challenges without having to compromise on performance, power, or size. Integrated level shifting designs are available in a wide assortment of I/O types, bit widths, data rate ranges, current drive capabilities, and package options. Texas Instruments’ portfolio of level shifter devices contains many different types of level translation functions that collectively can address almost any application requirement. TI’s level translation portfolio includes auto directional, direction controlled, and fixed direction level translators in industrial, automotive, and enhanced ratings.

For a list of recommended level translation devices for common interface types, see Table 1. Table 2 lists common FPGA families and target I/O levels that are often recommended for designed for power dissipation and the different interfaces supported by each family of devices that must be level shifted. For more information on all of TI’s level translation designs, see Voltage Translators & Level Shifters.