Product details

Technology Family AXC Applications GPIO Bits (#) 1 High input voltage (Min) (Vih) 0.455 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 0.65 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
Technology Family AXC Applications GPIO Bits (#) 1 High input voltage (Min) (Vih) 0.455 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 0.65 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
SOT-23 (DBV) 6 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 6 2 mm² 1.65 x 1.2 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 X2SON (DEA) 6 1 mm² 1 x 1 X2SON (DTQ) 6 1 mm² 1 x 0.8
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10 µA (85°C maximum) and 16 µA (125°C maximum)
  • Up to 500-Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100 mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 8000-V human body model
    • 1000-V charged-device model
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10 µA (85°C maximum) and 16 µA (125°C maximum)
  • Up to 500-Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100 mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100 mA per JESD 78, Class II
  • ESD protection exceeds JESD 22
    • 8000-V human body model
    • 1000-V charged-device model

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6 V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6 V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

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Technical documentation

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* Data sheet SN74AXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. D) PDF | HTML 15 Oct 2021
Application note Translate Voltages for MDIO PDF | HTML 16 Jul 2021
EVM User's guide AXC Small-Package Evaluation Module User's Guide (Rev. A) PDF | HTML 12 Jul 2021
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML 29 Mar 2021
Application note Translate Voltages for GPIO PDF | HTML 04 Aug 2020
Technical article A glitch in your system’s matrix? 11 Apr 2019
Application note How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter 28 Dec 2018
Application note Glitch free power sequencing with AXC level translators (Rev. A) 20 Sep 2018
Technical article Does your design have a low talker? 19 Mar 2018
Application note Evaluate SN74AXC1T45DRL Using A Generic EVM 06 Nov 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74AXC1T45 IBIS Model (Rev. A)

SCEM581A.ZIP (51 KB) - IBIS Model
Package Pins Download
SC70 (DCK) 6 View options
SOT-23 (DBV) 6 View options
SOT-5X3 (DRL) 6 View options
X2SON (DEA) 6 View options
X2SON (DTQ) 6 View options

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