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SN74AXC1T45

ACTIVE

Single-bit dual-supply bus transceiver

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Data sheet

SN74AXC1T45

ACTIVE
Data sheet Order now

Product details

Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 0.65 Vin (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 5 Technology family AXC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 1 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 0.65 Vin (max) (V) 3.6 Vout (min) (V) 0.65 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation Prop delay (ns) 5 Technology family AXC Supply current (max) (mA) 0.016 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) X2SON (DTQ) 6 0.8 mm² (1 mm × 0.8 mm) X2SON (DEA) 6 1 mm² (1 mm × 1 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm)
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model
  • Up and down translation across 0.65 V to 3.6 V
  • Operating temperature: –40°C to +125°C
  • Designed with glitch suppression circuitry to improve power sequencing performance
  • Maximum quiescent current (ICCA + ICCB) of 10µA (85°C maximum) and 16µA (125°C maximum)
  • Up to 500Mbps support when translating from 1.8 to 3.3V
  • VCC isolation feature:
    • If either VCC input is below 100mV, all I/Os outputs are disabled and become high-impedance
  • Ioff supports partial-power-down mode operation
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD protection exceeds JESD 22:
    • 8000-V human body model
    • 1000-V charged-device model

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.

The SN74AXC1T45 is a single-bit noninverting bus transceiver that uses two separate configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6V.

The DIR pin determines the direction of signal propagation. With the DIR pin configured HIGH, translation is from Port A to Port B. With DIR configured LOW, translation is from Port B to Port A. The DIR pin is referenced to VCCA, meaning that its logic-high and logic-low thresholds track with VCCA.

This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The VCC isolation feature ensures that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling their outputs.

The glitch suppression circuitry enables either supply rail to be powered on or off in any order, providing robust power sequencing performance.
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Technical documentation

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* Data sheet SN74AXC1T45 Single-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation datasheet (Rev. E) PDF | HTML Jan 12, 2024
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML Oct 2, 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML Jul 12, 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML Jul 3, 2024
Application brief Future-Proofing Your Level Shifter Design with TI's Dual Footprint Packages PDF | HTML Sep 5, 2023
Application brief Translate Voltages for MDIO PDF | HTML Jul 16, 2021
Selection guide Voltage Translation Buying Guide (Rev. A) Apr 15, 2021
Application note Low Voltage Translation for SPI, UART, RGMII, JTAG Interfaces (Rev. B) PDF | HTML Mar 29, 2021
Application note Translate Voltages for GPIO PDF | HTML Aug 4, 2020
Technical article Enabling IIoT to reach beyond the factory floor PDF | HTML Jul 29, 2020
Technical article A glitch in your system’s matrix? PDF | HTML Apr 11, 2019
Application brief How to Support 1.8-V Signals Using a 3.3-V LVDS Driver/Receiver + Level-Shifter Dec 28, 2018
Application note Glitch free power sequencing with AXC level translators (Rev. A) Sep 20, 2018
Application note Evaluate SN74AXC1T45DRL Using A Generic EVM Nov 6, 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Evaluation board

AVCLVCDIRCNTRL-EVM — Generic EVM for Direction-Controlled Bidirectional Translation Device Supporting AVC and LVC

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

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Simulation model

SN74AXC1T45 IBIS Model (Rev. A)

SCEM581A.ZIP (51 KB) - IBIS model
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 6 Ultra Librarian
SOT-23 (DBV) 6 Ultra Librarian
X2SON (DTQ) 6 Ultra Librarian
X2SON (DEA) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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