SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Table 12-536 provides details on the EDP_INTR_ASF[6:0] interrupts lines. Each of the interrupts listed in Table 12-536 has corresponding set of memory-mapped interrupt registers (status/mask/clear).
Interrupt Bit | Source | Description | Status Register | Mask Register | Clear Register |
---|---|---|---|---|---|
[6] | ECC_AGGR_DSC | ECC Aggregator Uncorrected Error Interrupt | EDP_ECC_DSC_DED_STATUS_REG0 | EDP_ECC_DSC_DED_ENABLE_SET_REG0 | EDP_ECC_DSC_DED_ENABLE_CLR_REG0 |
[5] | ECC_AGGR_PHY | ECC Aggregator Uncorrected Error Interrupt | EDP_ECC_PHY_DED_STATUS_REG0 | EDP_ECC_PHY_DED_ENABLE_SET_REG0 | EDP_ECC_PHY_DED_ENABLE_CLR_REG0 |
[4] | ECC_AGGR_CORE | ECC Aggregator Uncorrected Error Interrupt | EDP_ECC_CORE_DED_STATUS_REG0 | EDP_ECC_CORE_DED_ENABLE_SET_REG0 | EDP_ECC_CORE_DED_ENABLE_CLR_REG0 |
[3] | DSC | ASF Corrected interrupt detected in DSC | EDP_CORE_ENC_ASF_INT_STAT_P | EDP_CORE_ENC_ASF_INT_MASK_P | EDP_CORE_ENC_ASF_INT_CLR_P |
[2] | ASF Un-Corrected interrupt detected in DSC | ||||
[1] | MHDPTX Controller | ASF Corrected (NonFatal) event detected in MHDPTX Controller. Set if non-fatal error occurs. | EDP_CORE_ASF_INT_STATUS(1) | EDP_CORE_ASF_INT_MASK(1) | - |
[0] | ASF Un-corrected (Fatal) event detected in MHDPTX Controller. Set when fatal error occurs. |