SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Figure 12-69 shows the I/O interface signals of SERDES.
Although containing some of the basic external components, Figure 12-69 must not be considered as an exhaustive guide for the PCB designer. TI provides additional documents for those who are willing to design PCBs and/or fine tune the SerDes.
Table 12-134 describes the external signals of SERDES0 module.
Device Pin | I/O(1) | Description |
---|---|---|
SERDES0_RX0_P | I | SerDes differential data receive pins. Lane 0 |
SERDES0_RX0_N | I | |
SERDES0_TX0_P | O | SerDes differential data transmit pins. Lane 0 |
SERDES0_TX0_N | O | |
SERDES0_RX1_P | I | SerDes differential data receive pins. Lane 1 |
SERDES0_RX1_N | I | |
SERDES0_TX1_P | O | SerDes differential data transmit pins. Lane 1 |
SERDES0_TX1_N | O | |
SERDES0_RX2_P | I | SerDes differential data receive pins. Lane 2 |
SERDES0_RX2_N | I | |
SERDES0_TX2_P | O | SerDes differential data transmit pins. Lane 2 |
SERDES0_TX2_N | O | |
SERDES0_RX3_P | I | SerDes differential data receive pins. Lane 3 |
SERDES0_RX3_N | I | |
SERDES0_TX3_P | O | SerDes differential data transmit pins. Lane 3 |
SERDES0_TX3_N | O | |
PCIE_REFCLK1_P_OUT | O | Serdes Internal reference clock Output |
PCIE_REFCLK1_N_OUT | O | |
SERDES0_REFCLK_P | I | SerDes external system reference clock |
SERDES0_REFCLK_N | I | |
SERDES0_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. |