SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
Table 12-540 provides a summary of the bus interfaces and the MMR regions mapped to each interface in this module.
Region Name | Firewall Secure Mode Settings(1)(2) |
---|---|
INTG_CFG_VP | Should be Secure |
V2A_CORE_VP_REGS_APB | Secure (for Secure display) / Non-secure |
V2A_S_CORE_VP_REGS_SAPB | Must be Secure always (HDCP configuration) |
MHDPTX_WRAPPER_ECC_AGGR_CORE_CFG | Secure (for Secure display) / Non-secure |
MHDPTX_WRAPPER_ECC_AGGR_PHY_CFG | Secure (for Secure display) / Non-secure |
MHDPTX_WRAPPER_ECC_AGGR_DSC_CFG | Secure (for Secure display) / Non-secure |
Table 12-541 shows the MHDPTX Controller register/memory regions that are accessible during various operational modes:
Description | Address Base [19:0] | Register Bank | Direct access (x= APB (x= APB /SAPB) | Mailbox access (x= APB (x= APB /SAPB) | FW (uCPU) access | APB debug (Bootmode) access |
---|---|---|---|---|---|---|
Main configuration and Mailbox control registers. Each APB interface has its own set of these registers. | 0x00000 | APB_CFG | x | x | ||
Source digital PHY control | 0x00800 | SOURCE_PHY | x | x | x | |
Clocks and Reset | 0x00900 | SOURCE_CAR | x | x | x | |
Clock Meters | 0x00a00 | CLOCK_METERS | x | x | x | |
Video Interface 0 control | 0x00b00 | SOURCE_VIF | x | x | x | |
Video Interface 1 control | 0x00b20 | SOURCE_VIF | x | x | x | |
Video Interface 2 control | 0x00b40 | SOURCE_VIF | x | x | x | |
Video Interface 3 control | 0x00b60 | SOURCE_VIF | x | x | x | |
DPTX Digital PHY | 0x02000 | DPTX_PHY | x | x | x | |
DPTX HPD | 0x02100 | DPTX_HPD | x | x | x | |
DPTX Framer | 0x02200 | DPTX_FRAMER | x | x | x | |
DPTX Stream | 0x02200 | DPTX_STREAM | x | x | x | |
DPTX Main control | 0x02300 | DPTX_GLBL | x | x | x | |
DPTX HDCP SM | 0x02400 | DPTX_HDCP | x | x | x | |
DPTX Auxiliary | 0x02800 | DP_AUX | x | x | x | |
DPTX Stream 0 | 0x03000 | DPTX_STREAM | x | X | x | |
DPTX Stream 1 | 0x03080 | DPTX_STREAM | x | X | x | |
DPTX Stream 2 | 0x03100 | DPTX_STREAM | x | X | x | |
DPTX Stream 3 | 0x03080 | DPTX_STREAM | x | X | x | |
HDCP Crypto | 0x04000 | Crypto | x | x | - | |
HDCP Cipher | 0x05000 | Cipher Accessible only through SAPB mailbox | x (SAPB) | x | - | |
memory | 0x10000 …0x1ff00 | IMEM | x | x | ||
Data memory | 0x20000 …0x2ff00 | DMEM | x | x | ||
Audio decoder | 0x30000 | SOURCE_AIF_DECODER | APB | x | ||
SDP control stream 0 | 0x30800 | SOURCE_PIF | APB | x | ||
SDP control stream 1 | 0x30840 | SOURCE_PIF | APB | x | ||
SDP control stream 2 | 0x30880 | SOURCE_PIF | APB | x | ||
SDP control stream 3 | 0x308c0 | SOURCE_PIF | APB | x | ||
Registers related with IPS configuration | 0x30A00 | IPS_REGS | APB | x | ||
Fault reporting module | 0x30B00 | ASF | APB | x | ||
DSC encoder | 0x30C00 - 0x30F00 | DSC | APB | x |
Access Modes: