SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

4.2.4 Example 5 – Event Window

This example uses the counter, FSM, and HLC sub-modules of the CLB to implement an event timing feature which detects whether an interrupt service routine takes too long to respond to an interrupt. The example configures four PWM modules to operate in up-count mode and generate a low-to-high edge on a timer zero match event. The zero match event also triggers a PWM ISR which, for the purposes of this example, contains a dummy payload of variable length. At the end of the ISR, a write operation takes place to a CLB GP register to indicate the ISR has ended.

The PWM timer zero event is detected by a CLB module where it starts a timer. The timer “match 2” count is set as the maximum expected duration of the corresponding PWM ISR. If the GP register write does not take place before the match 2 count is reached, the HLC triggers a CLB interrupt. Four PWM modules and CLB tiles are configured similarly.

Figure 4-10 gives an outline of how one tile operates. The upper half shows the configuration of the PWM module to generate a fixed frequency waveform with rising edge on each counter zero match, and falling edge on compare A match. The zero match event generates a CPU interrupt and the objective is to trigger a CLB interrupt if the PWM ISR does not complete within a specified time.

GUID-2B094A29-5265-44BD-96D5-40B3C51123BD-low.gif Figure 4-10 Example 5: Event Window Configuration

The lower half shows the CLB counter, which commences counting at the start of the PWM ISR. If the ISR does not respond before the Match 2 value is reached, an interrupt is generated. The CLB ISR contains an “ESTOP” instruction which acts like a software break-point in the program.

To run the example, follow this procedure:

  1. In CCS v9.0 or higher, click “Project → Import CCS Projects…”
  2. Navigate to the CLB tool example directory. The path is:
    1. [C2000Ware]\driverlib\f2837xd\examples\cpu1\clb\ccs, or
    2. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or
    3. [C2000Ware]\driverlib\f2838x\examples\c28x\clb\ccs

    In the description that follows, it is assumed the C2000Ware directory above is in use.

  3. Select the project “clb_ex5_event_window”, and click “Finish”.
  4. In the CCS Project Explorer window, expand the project “clb_ex5_event_window” and open the file “clb_ex5_event_window.syscfg”.
  5. From the CCS menu, select “Project → Build Project”.

Open a CCS Expressions window and add the four program variables: “payload_x”, where ‘x’ is 1 to 4. Observe that at the start of the program, all payload variables have been set to 45. The payload is implemented as a ‘for’ loop in each PWM ISR, each iteration of which takes 12 cycles, so a payload of 45 corresponds to approximately 540 cycles.

Open the .syscfg file and inspect the match 2 settings in counter 0 of the four CLB modules. Notice that all timer limits are set to 3200.

Run the program with the default payloads and verify that the CLB interrupts to not trigger. Then, stop the program and increase any of the payloads. Re-run the program and determine whether any of the ISR limits is exceeded. Keep in mind that since the PWMs are not synchronized, the worst case ISR latency is the cumulative sum of all the payloads plus interrupt overheads.