SPRUIR8B april   2020  – july 2023

 

  1.   1
  2.   CLB Tool
  3.   Trademarks
  4. 1Introduction
    1. 1.1 CLB Tool Outline
    2. 1.2 Overview of the CLB Configuration Process
  5. 2Getting Started
    1. 2.1 CLB Related Collateral
    2. 2.2 Introduction
    3. 2.3 Installation
      1. 2.3.1 Installation to Compile SystemC
      2. 2.3.2 Install the Simulation Viewer
  6. 3Using the CLB Tool
    1. 3.1 Import the Empty CLB Project
    2. 3.2 Updating Variable Paths
    3. 3.3 Configuring a CLB Tile
    4. 3.4 Creating the CLB Diagram
    5. 3.5 Using the Simulator
      1. 3.5.1 The Statics Panel
      2. 3.5.2 Creating the Input Stimulus
      3. 3.5.3 Running the Simulation
      4. 3.5.4 Trace Signal Descriptions
  7. 4Examples
    1. 4.1 Foundational Examples
      1. 4.1.1  CLB Empty Project
      2. 4.1.2  Example 3 – PWM Generation
      3. 4.1.3  Example 7 – State Machine
      4. 4.1.4  Example 13 – PUSH-PULL Interface
      5. 4.1.5  Example 14 – Multi-Tile
      6. 4.1.6  Example 15 – Tile to Tile Delay
      7. 4.1.7  Example 16 - Glue Logic
      8. 4.1.8  Exampe 18 - AOC
      9. 4.1.9  Example 19 - AOC Release Control
      10. 4.1.10 Example 20 - CLB XBARs
    2. 4.2 Getting Started Examples
      1. 4.2.1  Example 1 – Combinatorial Logic
      2. 4.2.2  Example 2 – GPIO Input Filter
      3. 4.2.3  Example 4 – PWM Protection
      4. 4.2.4  Example 5 – Event Window
      5. 4.2.5  Example 6 – Signal Generation and Check
      6. 4.2.6  Example 8 – External AND Gate
      7. 4.2.7  Example 9 – Timer
      8. 4.2.8  Example 10 – Timer With Two States
      9. 4.2.9  Example 11 – Interrupt Tag
      10. 4.2.10 Example 12 – Output Intersect
      11. 4.2.11 Example 17 – One-Shot PWM Generation
      12. 4.2.12 Example 21 - Clock Prescaler and NMI
      13. 4.2.13 Example 22 - Serializer
      14. 4.2.14 Example 23 - LFSR
      15. 4.2.15 Example 24 - Lock Output Mask
      16. 4.2.16 Example 25 - Input Pipeline Mode
      17. 4.2.17 Example 26 - Clocking Pipeline Mode
    3. 4.3 Expert Examples
      1. 4.3.1 Example 27 - SPI Data Export
      2. 4.3.2 Example 28 - SPI Data Export DMA
      3. 4.3.3 Example 29 - Timestamp
      4. 4.3.4 Example 30 - Cyclic Redundancy Check
      5. 4.3.5 CLB TDM Serial Port
      6. 4.3.6 CLB LED Driver
      7. 4.3.7 FPGA/CPLD to C2000 Examples
  8. 5Enabling CLB Tool in Existing DriverLib Projects
  9. 6Frequently Asked Questions (FAQs)
  10. 7Revision History

4.2.3 Example 4 – PWM Protection

This example extends the features of example 1 to ensure an active high complementary pair PWM configuration always operates with a minimum value of dead-band irrespective of how the generating PWM module is configured. The example illustrates the configuration of four separate PWM tiles to implement PWM protection on four PWM modules. The outputs of PWM modules 1 to 4 are operated on by CLB tiles 1 to 4, respectively.

The protection functionality is enabled by the program variable “mode”. When set to 0 (the default condition), PWM signals are passed un-modified to the output pins. When set to 1, the PWM outputs are modified by the CLB to ensure dead-band.

To run the example, follow this procedure:

  1. In CCS v9.0 or higher, click “Project → Import CCS Projects…”
  2. Navigate to the CLB tool example directory. The path is:
    1. [C2000Ware]\driverlib\f2837xd\examples\cpu1\clb\ccs, or
    2. [C2000Ware]\driverlib\f28004x\examples\clb\ccs, or
    3. [C2000Ware]\driverlib\f2838x\examples\c28x\clb\ccs

    In the description that follows, it is assumed the C2000Ware directory above is in use.

  3. Select the project “clb_ex4_pwm_protection”, and click “Finish”.
  4. In the CCS Project Explorer window, expand the project “clb_ex4_pwm_protection” and open the file “clb_ex_pwm_protection.syscfg”.
  5. From the CCS menu, select “Project → Build Project”.
  6. Use an oscilloscope to observe the PWM signal pairs on the following pins of each LaunchPad/Docking Station board.
    Table 4-3 Example 4: Signal Connections
    PWM Tile F28379D LaunchPad F280049 LaunchPad F28388 Dock Station
    1A 1 J4/40 J8/60 49
    1B 1 J4/39 J8/59 51
    2A 2 J4/38 J8/56 53
    2B 2 J4/37 J8/55 55
    3A 3 J4/36 J4/36 50
    3B 3 J4/35 J4/35 52
    4A 4 J8/80 J8/58 54
    4B 4 J8/79 J8/57 56
  7. Open a CCS Expressions window and add the program variable “mode”.
  8. Run the program and verify that no dead-band exists between each PWM pair.
  9. Halt the program, change mode to 1, and run the program again. You should now observe rising edge dead-band between each PWM pair. The dead-band time is set by the match_1 values loaded into the two CLB counters, and has been set arbitrarily to 10 in this example.