Product details

Sample rate (max) (Msps) 25 Resolution (bps) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 177 Architecture Pipeline SNR (dB) 73.5 ENOB (bit) 11.9 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 25 Resolution (bps) 14 Number of input channels 4 Interface type Serial LVDS Analog input BW (MHz) 540 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 177 Architecture Pipeline SNR (dB) 73.5 ENOB (bit) 11.9 SFDR (dB) 92 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RTQ) 56 64 mm² 8 x 8
  • Quad Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer With Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible With 12-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)
  • Quad Channel
  • 14-Bit Resolution
  • Single Supply: 1.8 V
  • Serial LVDS Interface
  • Flexible Input Clock Buffer With Divide-by-1, -2, -4
  • SNR = 72.4 dBFS, SFDR = 87 dBc at
    fIN = 70 MHz
  • Ultra-Low Power Consumption:
    • 98 mW/Ch at 125 MSPS
  • Channel Isolation: 105 dB
  • Internal Dither and Chopper
  • Support for Multi-Chip Synchronization
  • Pin-to-Pin Compatible With 12-Bit Version
  • Package: VQFN-56 (8 mm × 8 mm)

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.

The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.

The ADC344x devices are a high-linearity, ultra-low power, quad-channel, 14-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization.

The ADC344x family supports serial low-voltage differential signaling (LVDS) to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 14-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are transmitted as LVDS outputs.

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Technical documentation

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* Data sheet ADC344x Quad-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters datasheet (Rev. B) PDF | HTML 17 Apr 2017
EVM User's guide ADC3xxxEVM and ADC3xJxxEVM User's Guide (Rev. D) 24 Aug 2018

Design & development

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Simulation model

ADC3444 IBIS Model

SLAM232.ZIP (36 KB) - IBIS Model
Simulation model

ADC3xxx Pspice Model

SLAM228.ZIP (15 KB) - PSpice Model
Simulation model

ADC3xxx TINA Model

SLAM226.ZIP (3 KB) - TINA-TI Spice Model
Simulation model

ADC3xxx TINA Reference Design

SLAM227.TSC (1083 KB) - TINA-TI Reference Design
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00499 — Transient and Digital Fault Recorder AFE Using Differential Amplifiers and HS ADC Reference Design

While Digital Fault Recorders (DFRs) can detect transients in 17/20 μs at 60/50 Hz, transient recorders capture disturbances that can peak and decay well within a microsecond. This reference design demonstrates the capturing of transient inputs at up to 1 MHz for DFR and 25 MHz for (...)
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VQFN (RTQ) 56 Ultra Librarian

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