The TLV571 is an 8-bit data acquisition system that combines a high-speed 8-bit ADC and a parallel interface. The device contains two on-chip control registers allowing control of software conversion start and power down via the bidirectional parallel port. The control registers can be set to a default mode using a dummy RD\ while WR\ is tied low allowing the registers to be hardware configurable.
The TLV571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the ADC is further powered down to only 10 uA.
Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal choice for high-speed digital signal processing.
|Part number||Order||Resolution (Bits)||Sample rate (Max) (kSPS)||Number of input channels||Interface||Operating temperature range (C)||Package Group||Approx. price (US$)||Power consumption (Typ) (mW)||Package size: mm2:W x L (PKG)||Architecture||Input type||Multi-channel configuration||Reference mode||Features||Input range (Max) (V)||Input range (Min) (V)||Analog voltage AVDD (Min) (V)||Analog voltage AVDD (Max) (V)||Digital supply (Min) (V)||Digital supply (Max) (V)||INL (Max) (+/-LSB)||SNR (dB)||THD (Typ) (dB)||Rating|
||8||125||1||Parallel||-40 to 85||
SOIC | 24
TSSOP | 24
|3.67 | 1ku||12||
24SOIC: 160 mm2: 10.3 x 15.5 (SOIC | 24)
24TSSOP: 34 mm2: 4.4 x 7.8 (TSSOP | 24)