TDA3 (ACTIVE)

SoC Processor for Advanced Driver Assist Systems (ADAS)

 

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This product family is available for high volume Automotive manufacturers. Please contact your TI sales representative for more details.

Learn more about the TDAx SoC for Advanced Driver Assistance Systems (ADAS).

Description

TI’s TDA3x System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). TDA3x SoC processors enable broad ADAS applications by integrating an optimal mix of performance, low power, smaller form factor and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience.

The TDA3x SoC enables sophisticated embedded vision technology in today’s automobile by enabling the industry’s broadest range of ADAS applications including front camera, rear camera, surround view, radar, and fusion on a single architecture.

The TDA3x SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processors (DSP), Vision AccelerationPac with Embedded Vision Engines (EVE), and dual ARM Cortex-M4 processors. TDA3x SoC also integrates a host of peripherals including multi-camera interfaces (both parallel and serial) for LVDS-based surround view systems, displays, CAN and GigB Ethernet AVB.

The EVE within the TDA3x Vision AccelerationPac offloads the vision analytics functionality from the processor while also reducing the power footprint. The Vision AccelerationPac is optimized for vision processing with a 32-bit RISC core for efficient program execution and a vector coprocessor for specialized vision processing.

Additionally, Texas Instruments provides a complete set of development tools for the ARM, DSP, and EVE coprocessor, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution.

The TDA3x SoC processor is qualified according to AEC-Q100 standard.

Features

  • Architecture Designed for ADAS Applications
  • Video and Image Processing Support
    • Full-HD Video (1920x1080p, 60 fps)
    • Video Input and Video Output
  • Up to two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C674x and C64x+
    • Up to Thirty-two 16 x 16-bit Fixed-point Multiplies per Cycle
  • Up to 512 kiB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • External Memory Interface (EMIF) Controller Module
    • DDR3/DDR3L up to DDR3-1066
      (ABF package only)
    • Up to 2-GiB Supported
  • Dual ARM® Cortex®-M4 Image Processor (IPU)
    • Dual-core, 212.8 MHz per Core
  • Vision AccelerationPac
    • Embedded Vision Engine (EVE)
  • Display Subsystem
    • Display Controller with DMA Engine
    • CVIDEO / SD-DAC TV analog composite output
  • Video Input Port (VIP) Module
    • Support for Up to 4 Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • Gigabit Ethernet (GMAC)
  • Dual Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Eight 32-Bit General-Purpose Timers
  • Three Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (MCSPIs)
  • Quad SPI Interface
  • Two Inter-Integrated Circuit (I2C) Ports
  • Multichannel Audio Serial Port (MCASP)
  • Up to 126 General-Purpose I/O (GPIO) Pins
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • Automotive AEC-Q100 Qualified
  • Seven Dual Clock Comparators (DCC)
  • Memory Cyclic Redundancy Check (CRC)
  • LBIST/PBIST Controler
  • Error Signaling Module (ESM)
  • Real Time Interrupt (RTI)
  • 10-bit ADC
  • ISP: Full HW image pipe: DPC, CFA, 3D-NF, RGB-YUV
    • i. WDR, HW LDC & Perspective
      (15x15 package)
  • 15 x 15mm, 0.65-mm Pitch, 367 Pin PBGA (ABF)

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