TIs KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNets capacity, so packet movement cannot be blocked by memory access.
HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its lowprotocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
|On-Chip L2 Cache|
|DSP MHz (Max.)|
|Other On-Chip Memory|
|Operating Temperature Range (C)|
|Approx. Price (US$)|
|Machine Vision||Machine Vision||Machine Vision|
|2 C66x||1 C66x||1 C66x|
|3072 KB (1024 KB Shared)||1024 KB (0 KB Shared)||2048 KB (1024 KB Shared)|
| 1000 |
|850|| 1000 |
|1024 KB||1024 KB||1024 KB|
|2 PCIe Gen2||2 PCIe Gen2||2 PCIe Gen2|
| -40 to 100 |
0 to 85
|0 to 85|| -40 to 100 |
0 to 85
|45.90 | 1ku||33.60 | 1ku||42.00 | 1ku|
|Sample & Buy||Sample & Buy||Sample & Buy|