Soft error rate FAQs

Find answers to basic questions about soft error rates (SERs), including possible causes, factors that affect the SER and how to estimate SER.

What is SER?

SER is soft error rate. Soft errors affect the data state of memories and sequential elements and are caused by random radiation events that occur naturally in the terrestrial environment.  In contrast to hard errors from defects or reliability wear-out mechanisms, soft errors do not typically damage the circuit itself (hence “soft” moniker) but corrupt the stored data or state of the circuit that is afflicted (in digital circuits this corresponds to a ones data state being erroneously flipped to a zero data state or vice versa).

Once new data is written to the memory location the data error is over-written and the system functions correctly. The failure rate induced by soft errors, or SER, is reported in FIT or FIT/Mbit (when focused on memory). In terms of occurrence rate, SER will be many times higher than the hard failure rate of all other mechanism combined. Soft errors are also referred to as a single-event upset (SEU) which better captures the idea that a single radiation event causes the data corruption.

What causes SER?

While there are many potential causes of SER, such as a glitch, noise, electromagnetic interference, the dominant cause of SER in well-designed circuits in a qualified manufacturing process are particle radiations.

In the terrestrial environment, the key radiations of concern are alpha particles emitted by trace impurities in the chip materials themselves (alpha particles cannot travel far and thus any alpha particles that reach the silicon are typically emitted from materials within the chip itself), and the ever-present cosmic-background neutron flux that bathes us at sea-level with ~ 13 n/hr-cm2 and at flight altitudes up to 26,000 n/hr-cm2. 

The alpha particle SER is minimized by the use of ultra-low alpha (ULA) materials but the neutrons, being very penetrating cannot easily be shielded, and thus we have to live with a certain level of SER. Further reduction in SER can only be achieved by the use of processes that reduce the amount of charge collected by radiation events (e.g. silicon on insulator) or more commonly, by the use of redundancy circuits (e.g. error correction in memories).

What factors affect SER?

Product technology affects SER to some level, but much more important is the amount of SRAM and sequential logic in the device. Usually devices with large unprotected memories have the highest SER.

Technologies that use reduced voltages for low-power tend to have higher SER since the data state is defined by the voltage and hence lower voltage means lower signal charge and hence the device becomes more sensitive to charge transients caused by radiation. The use of error correction on memory can greatly reduce SER. The use of ULA materials reduces the alpha particle component of SER.

Little can be done to shield the neutrons causing the remaining SER, and indeed, in avionics applications where the neutron flux is 100-1000s of times more intense than ground-level applications, the SER will be much higher.

Is there some acceptable level for SER?

No. There is no standard or “acceptable level” for SER. This is because “acceptable” SER depends on the application, how much memory is present, whether or not the memory is protected, where the device is operated (e.g. ground-level, aviation altitudes, etc.)

Because of these many factors in accessing the criticality of a bit failure, no single metric can be used for SER on a given general purpose part like a DSP, MSP, etc. The level of acceptable failure should be determined by the customer based on the product application, the software, and various applications details.

The first step to answering this specific question is that one should have some idea of an upper bound for the soft failure rate to judge if further work is needed.

How is the SER determined?

TI was one of the industry drivers of the JEDEC JESD89A “Measurement and reporting of alpha particle and terrestrial cosmic ray induced soft errors in semiconductor devices” test standard as a basis for doing radiation tests with alpha particles and neutrons.

We generally do not test products but designed test chips containing production SRAM arrays and sequential logic arrays to enable accurate modeling of SER. These are combined into an online SER estimator calculator that can be used to gauge the upper-bound for SER in any TI products made in CMOS technologies (350nm to 20nm). The calculator requires an NDA for external customers.