SBAS997A February   2020  – June 2021 ADC09DJ1300-Q1 , ADC09QJ1300-Q1 , ADC09SJ1300-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: DC Specifications
    6. 7.6  Electrical Characteristics: Power Consumption
    7. 7.7  Electrical Characteristics: AC Specifications
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Comparison
      2. 8.3.2 Analog Input
        1. Analog Input Protection
        2. Full-Scale Voltage (VFS) Adjustment
        3. Analog Input Offset Adjust
        4. ADC Core
          1. ADC Core Calibration
          2. ADC Theory of Operation
          3. Analog Reference Voltage
          4. ADC Over-range Detection
          5. Code Error Rate (CER)
        5. Temperature Monitoring Diode
        6. Timestamp
        7. Clocking
          1. Converter PLL (C-PLL) for Sampling Clock Generation
          2. LVDS Clock Outputs (PLLREFO±, TRIGOUT±)
          3. Optional CMOS Clock Outputs (ORC, ORD)
          4. SYSREF for JESD204C Subclass-1 Deterministic Latency
            1. SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
            2. SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
        8. JESD204C Interface
          1.  Transport Layer
          2.  Scrambler
          3.  Link Layer
          4.  8B/10B Link Layer
            1. Data Encoding (8B/10B)
            2. Multiframes and the Local Multiframe Clock (LMFC)
            3. Code Group Synchronization (CGS)
            4. Initial Lane Alignment Sequence (ILAS)
            5. Frame and Multiframe Monitoring
          5.  64B/66B Link Layer
            1. 64B/66B Encoding
            2. Multiblocks, Extended Multiblocks and the Local Extended Multiblock Clock (LEMC)
              1. Block, Multiblock and Extended Multiblock Alignment using Sync Header
                1. Cyclic Redundancy Check (CRC) Mode
                2. Forward Error Correction (FEC) Mode
            3. Initial Lane Alignment
            4. Block, Multiblock and Extended Multiblock Alignment Monitoring
          6.  Physical Layer
            1. SerDes Pre-Emphasis
          7.  JESD204C Enable
          8.  Multi-Device Synchronization and Deterministic Latency
          9.  Operation in Subclass 0 Systems
          10. Alarm Monitoring
            1. Clock Upset Detection
            2. FIFO Upset Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Mode and High Performance Mode
      2. 8.4.2 JESD204C Modes
        1. JESD204C Transport Layer Data Formats
        2. 64B/66B Sync Header Stream Configuration
        3. Redundant Data Mode (Alternate Lanes)
      3. 8.4.3 Power-Down Modes
      4. 8.4.4 Test Modes
        1.  Serializer Test-Mode Details
        2.  PRBS Test Modes
        3.  Clock Pattern Mode
        4.  Ramp Test Mode
        5.  Short and Long Transport Test Mode
          1. Short Transport Test Pattern
        6.  D21.5 Test Mode
        7.  K28.5 Test Mode
        8.  Repeated ILA Test Mode
        9.  Modified RPAT Test Mode
        10. Calibration Modes and Trimming
          1. Foreground Calibration Mode
          2. Background Calibration Mode
          3. Low-Power Background Calibration (LPBG) Mode
        11. Offset Calibration
        12. Trimming
    5. 8.5 Programming
      1. 8.5.1 Using the Serial Interface
      2. 8.5.2 SCS
      3. 8.5.3 SCLK
      4. 8.5.4 SDI
      5. 8.5.5 SDO
      6. 8.5.6 Streaming Mode
    6. 8.6 SPI_Register_Map Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Light Detection and Ranging (LiDAR) Digitizer
        1. Design Requirements
        2. Detailed Design Procedure
          1. Analog Front-End Requirements
          2. Calculating Clock and SerDes Frequencies
        3. Application Curves
        4. Quad Channel Hand-Held 1.25-GSPS 625-MSPS Oscilloscope
      2. 9.2.2 Initialization Set Up
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Documentation Support
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Multi-Device Synchronization and Deterministic Latency

JESD204C subclass 1 outlines a method to achieve deterministic latency across the serial link. If two devices achieve the same deterministic latency then they can be considered synchronized. This latency must be achieved from system startup to startup to be deterministic. There are two key requirements to achieve deterministic latency. The first is proper capture of SYSREF for which the device provides a number of features to simplify this requirement at giga-sample clock rates (see the SYSREF Capture section for more information). SYSREF resets either the LMFC in 8B/10B encoding mode or the LEMC is 64B/66B encoding mode. The LMFC and LEMC are analogous between the two modes and is now referred to as LMFC/LEMC.

The second requirement is to choose a proper elastic buffer release point in the receiver. Because the device is an ADC, the device is the transmitter (TX) in the JESD204C link and the logic device is the receiver (RX). The elastic buffer is the key block for achieving deterministic latency, and does so by absorbing variations in the propagation delays of the serialized data as the data travels from the transmitter to the receiver. A proper release point is one that provides sufficient margin against delay variations. An incorrect release point results in a latency variation of one LMFC/LEMC period. Choosing a proper release point requires knowing the average arrival time of data at the elastic buffer, referenced to an LMFC/LEMC edge, and the total expected delay variation for all devices. With this information the region of invalid release points within the LMFC/LEMC period can be defined, which stretches from the minimum to maximum delay for all lanes. Essentially, the designer must ensure that the data for all lanes arrives at all devices after the previous release point occurs and before the next release point occurs.

Figure 8-11 provides a timing diagram that demonstrates this requirement. In this figure, the data for two ADCs is shown. The second ADC has a longer routing distance (tPCB) and results in a longer link delay. First, the invalid region of the LMFC/LEMC period is marked off as determined by the data arrival times for all devices. Then, the release point is set by using the release buffer delay (RBD) parameter to shift the release point an appropriate number of frame clocks from the LMFC/LEMC edge so that the release point occurs within the valid region of the LMFC/LEMC cycle. In the case of Figure 8-11, the LMFC/LEMC edge (RBD = 0) is a good choice for the release point because there is sufficient margin on each side of the valid region.

GUID-22F8CC43-770F-4A6C-A82C-2956FF815186-low.gifFigure 8-11 LMFC/LEMC Valid Region Definition for Elastic Buffer Release Point Selection

The TX and RX LMFC/LEMCs do not necessarily need to be phase aligned, but knowledge of their phase is important for proper elastic buffer release point selection. Also, the elastic buffer release point occurs within every LMFC/LEMC cycle, but the buffers only release when all lanes have arrived. Therefore, the total link delay can exceed a single LMFC/LEMC period; see JESD204B multi-device synchronization: Breaking down the requirements for more information.