ADC09QJ1300-Q1

ACTIVE

Product details

Sample rate (Max) (MSPS) 1300 Resolution (Bits) 9 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (Bits) 8.5 SFDR (dB) 64 Operating temperature range (C) -40 to 125 Input buffer Yes
Sample rate (Max) (MSPS) 1300 Resolution (Bits) 9 Number of input channels 4 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Input range (Vp-p) 0.8 Power consumption (Typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 53.5 ENOB (Bits) 8.5 SFDR (dB) 64 Operating temperature range (C) -40 to 125 Input buffer Yes
FCBGA (AAV) 144 100 mm² 10 x 10
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 450 mW / channel
    • Dual channel: 625 mW / channel
    • Single channel: 940 mW
  • Power supplies: 1.1 V, 1.9 V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 9 Bit
    • Maximum sampling rate: 1.3 GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (100 MHz): 53.5 dBFS
    • ENOB (100 MHz): 8.5 Bits
    • SFDR (100 MHz): 64 dBc
    • Noise floor (–20 dBFS): –143 dBFS
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1 GSPS):
    • Quad Channel: 450 mW / channel
    • Dual channel: 625 mW / channel
    • Single channel: 940 mW
  • Power supplies: 1.1 V, 1.9 V

ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4 GHz.

ADC09xJ1300-Q1 is a family of quad, dual and single channel, 9-bit, 1.3 GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems. ADC09xJ1300-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4 GHz.

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Technical documentation

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Type Title Date
* Data sheet ADC09xJ1300-Q1 Quad/Dual/Single Channel, 1.3-GSPS, 9-bit Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) 21 Jun 2021
Technical article How smart AFEs offer an integrated analog solution for thermoelectric cooling control 04 Jan 2022
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
User guide ADCxxQJ1x00 Evaluation Module User's Guide 21 Apr 2019
Technical article How to achieve fast frequency hopping 03 Mar 2019
Technical article RF sampling: Learning more about latency 09 Feb 2017

Design & development

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Evaluation board

ADC09QJ1300EVM — ADC09QJ1300 evaluation module for quad-channel, 9-bit, 1.3-GSPS ADC with JESD204C interface

The ADC09QJ1300 evaluation module (EVM) allows for the evaluation of the ADC09QJ1300-Q1 device. ADC09QJ1300-Q1 is a low-power, 9-bit, quad-channel, 1.3-GSPS analog-to-digital converter (ADC) with a buffered analog input and integrated digital down converter with on-chip PLL, which features a (...)

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