SBAS958A December 2019 – June 2020 ADC3421-Q1
PRODUCTION DATA.
Table 3 lists the location, value, and functions of performance mode registers in the device.
MODE | REGISTER SETTINGS | DESCRIPTION |
---|---|---|
Special modes | Registers 139 (bit 3), 239 (bit 3), 439 (bit 3), and 539 (bit 3) | Always write 1 for best performance |
Disable dither | Registers 1 (bits 7:0), 134 (bits 5 and 3), 234 (bits 5 and 3),
434 (bits 5 and 3), and 534 (bits 5 and 3) |
Disable dither to improve SNR |
Disable chopper | Registers 122 (bit 1), 222 (bit 1), 422 (bit 1), and 522 (bit 1) | Disable chopper (shifts 1/f noise floor at dc) |
High IF modes | Registers 11Dh (bit 1), 21Dh (bit 1), 31Dh (bit 7 and bit 1), 41Dh (bit 1), 51Dh (bit 1), 308h (bits 7-6), 608h (bits 7-6) and 61Dh (bit 7 and bit 1) | Improves HD3 by a couple of dB for IF > 100 MHz |