SLAS708A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949


  1. Features
  2. Applications
  3. Description
    1.     ADS794x Block Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

16-Clock Frame

Figure 47 through Figure 49 illustrate the devices operating in 16-clock mode. This mode is the fastest mode for device operation. In this mode, the devices output data from previous conversions while converting the recently sampled signal.

As shown in Figure 47, the ADS7947 starts acquisition of the analog input from the 14th rising edge of SCLK. The device samples the input signal on the CS falling edge. SDO comes out of 3-state and the device outputs the MSB on the CS falling edge. The device outputs the next lower SDO bits on every SCLK falling edge after the SCLK rising edge. The data correspond to the sample and conversion completed in the previous frame. During a CS low period, the device converts the recently sampled signal and uses SCLK for conversions. The number of clocks needed for a conversion for 12-bit and 8-bit devices are different. For the ADS7947, conversion is complete on the 14th SCLK rising edge. CS can be high at any time after the 14th SCLK rising edge. The CS rising edge after the 14th SCLK rising edge and before the 29th SCLK falling edge keeps the device in the 16-clock data frame. The device output goes to 3-state with CS high.

ADS7947 ADS7948 ADS7949 ai_tim_16clk_no_pdwn_las708.gifFigure 47. ADS7947 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)

SCLK can also be stopped after the 14th SCLK rising edge.

Figure 48 and Figure 49 illustrate the 16-clock mode operation for the ADS7948 and ADS7949, respectively. The operation for these 10-bit and 8-bit devices is identical to the ADS7947 except that the conversion ends on different edges of SCLK. For the ADS7948, the conversion ends and acquisition starts on the 11th SCLK rising edge. For the ADS7949, the device uses the ninth SCLK rising edge for the conversion end and acquisition start. Similar to the ADS7947, CS can go high and SCLK can be stopped when the device enters acquisition.

ADS7947 ADS7948 ADS7949 ai_tim_16clk_7948_las708.gifFigure 48. ADS7948 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)
ADS7947 ADS7948 ADS7949 ai_tim_16clk_7949_las708.gifFigure 49. ADS7949 Operating in 16-Clock Mode Without Power-Down (PDEN = 0)