SLAS708A September   2010  – September 2019 ADS7947 , ADS7948 , ADS7949


  1. Features
  2. Applications
  3. Description
    1.     ADS794x Block Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions: ADS794x (12-, 10-, 8-Bit)
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS7947 (12-Bit)
    6. 7.6  Electrical Characteristics: ADS7948 (10-Bit)
    7. 7.7  Electrical Characteristics: ADS7949 (8-Bit)
    8. 7.8  Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics: ADS7947, ADS7948, ADS7949
    11. 7.11 Typical Characteristics: ADS7947 (12-Bit)
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer and ADC Input
      2. 8.3.2 Reference
      3. 8.3.3 Clock
      4. 8.3.4 ADC Transfer Function
      5. 8.3.5 Power-Down
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Operation
    5. 8.5 Programming
      1. 8.5.1 16-Clock Frame
      2. 8.5.2 32-Clock Frame
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving an ADC Without a Driving Op Amp
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Multiplexer and ADC Input

The devices feature pseudo-differential inputs with a double-pole, double-throw multiplexer. The negative inputs (AINxN) can accept swings of ±0.2 V; the positive inputs (AINxP) allow signals in the range of 0 V to VREF over the negative input. The ADC converts the difference in voltage: VAINxP – VAINxN. This feature can be used in multiple ways.

Two signals can be connected from different sensors with unequal ground potentials (within ±0.2 V) to a single ADC. The pseudo-differential ADC rejects common-mode offset and noise. This feature also allows the use of a single-supply op amp. The signal and the AINxN input can be offset by +0.2 V, which provides the ground clearance needed for a single-supply op amp.

Figure 39 shows the electrostatic discharge (ESD) diodes to supply and ground at every analog input. Make sure that these diodes do not turn on by keeping the supply voltage within the specified input range.

ADS7947 ADS7948 ADS7949 ai_ana_in_fbd_las708.gifFigure 39. Analog Inputs

Figure 40 shows an equivalent circuit of the multiplexer and ADC sampling stage. The positive and negative inputs are separately sampled on 32-pF sampling capacitors. The multiplexer and sampling switches are represented by an ideal switch in series with a 12-Ω resistance. During sampling, the devices connect the 32-pF sampling capacitor to the ADC driver. This connection creates a glitch at the device input. TI recommends connecting a capacitor across the AINxP and AINxN terminals to reduce this glitch. A driving circuit must have sufficient bandwidth to settle this glitch within the acquisition time.

ADS7947 ADS7948 ADS7949 ai_equiv_cir_input_las708.gifFigure 40. Input Sampling Stage Equivalent Circuit
(See the Application Information section for details on the driving circuit.)

Figure 41 shows a timing diagram for the ADC analog input channel selection. As shown in Figure 41, the CH SEL signal selects the analog input channel to the ADC. CH SEL = 0 selects channel 0 (AIN0P – AIN0N) and CH SEL = 1 selects channel 1 (AIN1P – AIN1N). It is recommended not to toggle the CH SEL signal during an ADC acquisition phase until the device detects the first valid SCLK rising edge after the device samples the analog input. If CH SEL is toggled during this period, an erroneous output code can result because the device might detect an unsettled analog input.

CH SEL can be toggled at any time during the window specified in Figure 41; however, TI recommends selecting the desired channel after the first SCLK rising edge and before the second SCLK rising edge. This timing ensures that the multiplexer output is settled before the ADC starts acquisition of the analog input.

ADS7947 ADS7948 ADS7949 ai_tim_adc_ch_select_las708.gif


N indicates the 14th SCLK rising edge for the ADS7947 (12 bit), the 11th rising edge for the ADS7948 (10 bit), and the ninth rising edge for the ADS7949 (8 bit).
Figure 41. ADC Analog Input Channel Selection