CS can be held low past the 16th falling edge of SCLK. The device continues to output recently converted data starting with the 16th SCLK falling edge. If CS is held low until the 30th SCLK falling edge, then the device detects 32-clock mode. The device data from recent conversions are already out with no latency before the 30th SCLK falling edge. When 32-clock mode is detected, the device outputs 16 zeros during the next conversion (in fact, for the first 16 clocks), unlike 16-clock mode where the device outputs the previous conversion result. SCLK can be stopped after the device has seen the 30th falling edge with CS low.