The device employs a sample-and-hold stage at the input; see Figure 40 for a typical equivalent circuit of a sample-and-hold stage. The device connects a 32-pF sampling capacitor during sampling. This configuration results in a glitch at the input terminals of the device at the start of the sample. The external circuit must be designed in such a way that the input can settle to the required accuracy during the sampling time chosen. Figure 53 shows a typical driving circuit for the analog inputs.
The 470-pF capacitor across the AINxP and AINxN terminals decouples the driving op amp from the sampling glitch. Splitting the series resistance of the input filter in two equal values is recommended, as shown in Figure 53. Both input terminals are recommended to have the same impedance from the external circuit. The low-pass filter at the input limits noise bandwidth of the driving op amp. Select the filter bandwidth so that the full-scale step at the input can settle to the required accuracy during the sampling time. Equation 1, Equation 2, and Equation 3 are useful for filter component selection.
Also, make sure the driving op amp bandwidth does not limit the signal bandwidth below filter bandwidth. In many applications, signal bandwidth can be much lower than filter bandwidth. In this case, an additional low-pass filter can be used at the input of the driving op amp. This signal filter bandwidth can be selected in accordance with the input signal bandwidth.