SBAS707B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process uses an internal clock. The device ignores any further transitions on the CONVST signal until the ongoing conversion is complete (that is, during the time interval of tconv).
At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:
The conversion time, tconv, varies within the specified limits of tconv_min and tconv_max (as specified in the Switching Characteristics table). After initiating a conversion, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the tconv_max duration to elapse before initiating a new operation (data transfer or conversion). If RVS is not monitored, substitute tconv in Equation 4 with tconv_max.