SBAS707B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Ease of System Design With ADS89xxB Integrated Features
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. Sample-and-Hold Circuit
        2. Internal Oscillator
        3. ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. Protocols for Configuring the Device
        2. Protocols for Reading From the Device
          1. Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. SPI-Compatible Protocols with Bus Width Options
          3. Source-Synchronous (SRC) Protocols
            1. Output Clock Source Options with SRC Protocols
            2. Bus Width Options With SRC Protocols
            3. Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. Single Device: All multiSPI Options
        2. Single Device: Minimum Pins for a Standard SPI Interface
        3. Multiple Devices: Daisy-Chain Topology
        4. Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. Charge-Kickback Filter
        2. Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Reference Buffer Module

On the CONVST rising edge, the device moves from ACQ state to CONV state, and the internal capacitors are switched to the REFBUFOUT pins as per the successive approximation algorithm. Most of the switching charge required during the conversion process is provided by external decoupling capacitor CREFBUF. If the charge lost from the CREFBUF is not replenished before the next CONVST rising edge, the voltage on REFBUFOUT pins is less than VREFBUFOUT. The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the output code. The internal reference buffer of the device maintains the voltage on REFBUFOUT pins within 0.5-LSB of VREFBUFOUT. All the performance characteristics of the device are specified with the internal reference buffer and specified values of CREFBUF and RESR.

In burst-mode of operation, the device stays in ACQ state for a long duration of time and then performs a burst of conversions. During the acquisition state (ACQ), the sampling capacitor (CS) is connected to the differential input pins and no charge is drawn from the REFBUFOUT pins. However, during the very first conversion cycle, there is a step change in the current drawn from the REFBUFOUT pins. This sudden change in load triggers a transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end of the conversion cycle results in a change in output codes over the subsequent conversions, as shown in Figure 31. The internal reference buffer of the ADS89xxB, when used with the recommended values of CREFBUF and RESR, keeps the transient settling error at the end of each conversion cycle within 0.5-LSB. Therefore, the device supports burst-mode of operation with every conversion result being as per the datasheet specifications.

ADS8910B ADS8912B ADS8914B REFBUF_Settling_SBAS707.gifFigure 31. ADC Output Codes in Burst-Mode Operation With Various ADC Reference Buffers

Figure 32 shows the block diagram of the internal reference buffer.

ADS8910B ADS8912B ADS8914B ref_module_sbas707.gifFigure 32. Internal Reference Buffer Block Diagram

The input range for the device is set by the external voltage applied at the REFIN pin (VREF). The REFIN pin has electrostatic discharge (ESD) protection diodes to the RVDD and GND pins. For minimum input offset error (see E(IO) specified in the Electrical Characteristics), set the REF_SEL[2:0] bits to the value closest to VREF (see the OFST_CAL register).

The internal reference buffer has a typical gain of 1 V/V with minimal offset error (see V(RO) specified in the Electrical Characteristics), and the output of the buffer is available between the REFBUFOUT pins and the REFM pins. Set the REF_OFST[4:0] bits to add or subtract an intentional offset voltage (see the REF_MRG register).

Figure 33 shows the external connections required for the internal reference buffer.

ADS8910B ADS8912B ADS8914B ref_connection_sbas707.gifFigure 33. External Connections for the Internal Reference Buffer

Select RREF_FLT and CREF_FLT to limit the broadband noise contribution from the external reference source. The device takes very little current, IREF, from the REFIN pin (typically, 0.1 µA). However, this current flows through RREF_FLT and may result in additional gain error.

Short the two REFBUFOUT pins externally. Short the two REFM pins to GND externally. As shown in Figure 33, place a combination of RESR and CREFBUF (see the Electrical Characteristics) between the REFBUFOUT pins and the REFM pins as close to the device as possible. See the Layout section for layout recommendations.