SBAS707B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
PRODUCTION DATA.
The host controller operates the device at the desired throughput by interleaving the conversion cycles and the data transfer frames.
The cycle time of the device, t_{cycle}, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, t_{resp}, is the time difference between the host controller initiating conversion C, and the host controller receiving the complete result for conversion C.
Figure 44 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising edge at time t = 0, and the conversion result becomes available for data transfer at t_{conv}. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of conversion C + 1 (that is, before t_{cycle} + t_{conv}).
To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle during the quiet acquisition time (t_{qt_acq}) and quiet aperture time (t_{d_cnvcap}). Any noise during t_{d_cnvcap} may negatively affect the result of the ongoing conversion, whereas any noise during t_{qt_acq} may negatively affect the result of the subsequent conversion.
This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion. Zone 1 and zone 2 for conversion C are defined in Table 3.
ZONE | STARTING TIME | ENDING TIME |
---|---|---|
Zone 1 for conversion C | ||
Zone 2 for conversion C |
The response time includes the conversion time and the data transfer time, and thus is a function of the selected data transfer zone.
Figure 45 and Figure 46 illustrate interleaving of three conversion cycles (C, C + 1, and C + 2) with three data transfer frames (F, F + 1, and F + 2) in zone 1 and in zone 2, respectively.
To achieve cycle time t_{cycle}, the read time in zone 1 is given by Equation 5:
For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:
Then, the zone 1 data transfer achieves a response time defined by Equation 7:
At lower SCLK speeds, t_{read-Z1} increases, resulting in slower response times and higher cycle times.
To achieve the same cycle time, t_{cycle}, the read time in zone 2 is given by Equation 8:
For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:
Then, the zone 2 data transfer achieves a response time defined by Equation 10:
Any increase in t_{read-Z2} increases response time and may increase cycle time.
For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7); whereas, the zone 2 data transfer clearly requires a lower SCLK speed but has a slower response time (as evident from Equation 8, Equation 9, and Equation 10). For more information about benefits of zone 2 data transfer when using isolated digital interface or MCU refer to TI TechNote - Simplify Isolation Designs Using an Enhanced-SPI ADC Interface.
NOTE
A data transfer frame can begin in zone 1, and then extend into zone 2; however, the host controller must make sure that no digital transitions occur during the t_{qt_acq} and t_{d_cnvcap} time intervals.
NOTE
For data transfer operations in zone 2 using the ADC-Clock-Master protocol
(SDO_MODE[1:0] = 11b), the device supports only the external-clock-echo option
(SSYNC_CLK_SEL[1:0] = 00b); see Table 9.