In any data transfer frame, the contents of an internal, 22-bit, output data word are shifted out on the SDO pins. The D[21:4] bits of the 22-bit output data word for any frame F + 1, are determined by:
If a valid RD_REG command is executed in frame F, then the D[21:14] bits in frame F + 1 reflect the contents of the selected register, and the D[13:0] bits are zeros.
If the DATA_VAL bit for frame F + 1 is set to 1, then the D[21:4] bits in frame F + 1 are replaced by the DATA_PATN[17:0] bits.
For all other combinations, the D[21:4] bits for frame F + 1 are the latest conversion result.
With the PAR_EN bit set to 0, the D and D bits of the output data word are set to 0 (default configuration).
When the PAR_EN bit is set to 1, the device calculates the parity bits (FLPAR and FTPAR) and appends them as bits D and D.
See the DATA_CNTL register for more details on the FPAR_LOC[1:0] bit settings. Bits D[1:0] are set to 00b.