This device family features nine configuration registers (as described in the Register Maps section). To access the internal configuration registers, these devices support the commands listed in Table 2.
|B[21:17]||B[16:8]||B[7:0]||COMMAND ACRONYM||COMMAND DESCRIPTION|
|10000||<9-bit address>||<8-bit unmasked bits>||CLR_BITS||Clear <8-bit unmasked bits> from <9-bit address>|
|10001||<9-bit address>||00000000||RD_REG||Read contents from the <9-bit address>|
|10010||<9-bit address>||<8-bit data>||WR_REG||Write <8-bit data> to the <9-bit address>|
|10011||<9-bit address>||<8-bit unmasked bits>||SET_BITS||Set <8-bit unmasked bits> from <9-bit address>|
|Remaining combinations||xxxxxxxxx||xxxxxxxx||Reserved||These commands are reserved and treated by the device as no operation|
These devices support two types of data transfer operations: data write (the host controller configures the device), and data read (the host controller reads data from the device).
Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The WR_REG command writes the 8-bit data into the 9-bit address specified in the command string. The CLR_BITS command clears the specified bits (identified by 1) at the 9-bit address (without affecting the other bits), and the SET_BITS command sets the specified bits (identified by 1) at the 9-bit address (without affecting the other bits).
The data read from the device can be synchronized to the same external clock or to an internal clock of the device by programming the configuration registers (see the Data Transfer Protocols section for details).