SBASA74A January 2023 – April 2024 ADS9218 , ADS9219
ADVMIX
The ADS921x features a built-in decimation filter that averages the conversion results from the ADC. The output data rate is reduced with higher data averaging. Table 6-3 shows the register settings corresponding to oversampling ratios.
As shown in Figure 6-4, a pulse on the SMPL_SYNC pin resets the decimation filter. A pulse on SMPL_SYNC synchronizes multiple ADS921x devices when using the decimation filter.
DECIMATION | REGISTER | VALUE |
---|---|---|
OSR initialization | CLK3 (0xC5[9]) | 1 |
OSR_INIT1 (0xC0[11:10]) | 0 for DATA_LANES = 5 or 7 1 for DATA_LANES = 0 or 2 |
|
OSR_INIT2 (0xC4[5:4]) | 2 | |
OSR_INIT3 (0xC4[1]) | 1 | |
OSR_EN (0x0D[6]) | 1 | |
2 | OSR (0x0D[5:2]) | 0 |
OSR_CLK (0xC0[9:7]) | 0 | |
4 | OSR (0x0D[5:2]) | 1 |
OSR_CLK (0xC0[9:7]) | 4 | |
8 | OSR (0x0D[5:2]) | 2 |
OSR_CLK (0xC0[9:7]) | 5 | |
16 | OSR (0x0D[5:2]) | 3 |
OSR_CLK (0xC0[9:7]) | 6 |