SBASA74A January 2023 – April 2024 ADS9218 , ADS9219
ADVMIX
Use a low-jitter external clock with a high slew rate to maximize SNR performance. Operate the ADS921x with a differential or single-ended clock input. Clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, provide a clock signal with fast slew rates that maximizes swing between IOVDD and GND levels.
The sampling clock must be a free-running continuous clock. The ADC generates a valid output data, data clock, and frame clock tPU_SMPL_CLK, as specified in the Switching Characteristics after a free-running sampling clock is applied. The ADC output data, data clock, and frame clock are invalid when the sampling clock is stopped.
Figure 6-8 shows a diagram of the differential sampling clock input. For this configuration, connect the differential sampling clock input to the SMPL_CLKP and SMPL_CLKM pins. Figure 6-9 shows a diagram of the single-ended sampling clock input. In this configuration, connect the single-ended sampling clock to SMPL_CLKP and connect SMPL_CLKM to ground.