SBASA74A January   2023  – April 2024 ADS9218

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9219
    11. 5.11 Typical Characteristics
    12. 5.12 Typical Characteristics: ADS9217
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 Fixed Pattern
          2. 6.3.8.3.2 Alternating Test Pattern
          3. 6.3.8.3.3 Digital Ramp
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

at AVDD_5V = 4.75V to 5.25V for ADS9219, and ADS9218, and AVDD_5V = 4.5V to 5.5V for ADS9217, VDD_1V8 = 1.75V to 1.85V, internal VREF = 4.096V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IB Input bias current 0.5 TBD µA
Input bias current thermal drift 1 nA/℃
DC PERFORMANCE
Resolution No missing codes 18 Bits
DNL Differential nonlinearity –0.75 ±0.4 0.75 LSB
INL Integral nonlinearity TA = 0°C to 70°C, ADS9217 and ADS9218 –1.5 ±0.8 1.5 LSB
–5.7 ±3 5.7 ppm
TA = –40°C to 125°C, ADS9217 and ADS9218 –2 ±0.8 2 LSB
–7.6 ±3 7.6 ppm
ADS9219 at 20MSPS TBD ±1 TBD LSB
TBD ±3.8 TBD ppm
ADS9219 up to 16MSPS TBD ±0.8 TBD LSB
TBD ±3.8 TBD ppm
V(OS) Input offset error ±20 LSB
dVOS/dT Input offset error thermal drift ±0.5 1.5 ppm/°C
GE Gain error(1) –0.05 ±0.01 0.05 %FSR
dGE/dT Gain error thermal drift(1) ±1 2 ppm/°C
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2kHz 95 dB
fIN = 1MHz 94
SNR Signal-to-noise ratio fIN = 2kHz 95.5 dB
fIN = 1MHz 94.9
THD Total harmonic distortion fIN = 2kHz, ADS9217 and ADS9218 –118 dB
fIN = 2kHz, ADS9219 at 20MSPS –110
fIN = 2kHz, ADS9219 up to 16MSPS –118
fIN = 1MHz, all devices –104
SFDR Spurious-free dynamic range fIN = 2kHz 120 dB
fIN = 1MHz 104
Isolation crosstalk fIN = 2kHz TBD dB
Aperture jitter 0.3 psRMS
BW Input Bandwidth (–3dB) ADS9219 135 MHz
ADS9218 90
ADS9217 45
COMMON-MODE OUTPUT BUFFER
VCMOUT Common-mode output voltage 2.2 2.4 2.65 V
Output current drive 0 5 μA
LVDS RECEIVER (SMPL_CLK)
VTH High-level input voltage (P – M) AC coupled 300 mV
DC coupled 100
VTL Low-level input voltage (P – M) AC coupled –300 mV
DC coupled –100
VICM Input common-mode voltage 0.5 1.2 1.4 V
LVDS OUTPUT (CLKOUT, DOUTA, and DOUTB)
VODIFF Differential output voltage RL = 100Ω TBD 350 TBD mV
VOCM Output common-mode voltage RL = 100Ω 1.08 1.1 1.32 V
CMOS INPUTS (CS, SCLK, and SDI)
VIL Input low logic level –0.1 0.5 V
VIH Input high logic level 1.3 VDD_1V8 V
CMOS OUTPUT (SDO)
VOL Output low logic level IOL = 200µA sink 0 0.4 V
VOH Output high logic level IOH = 200µA source 1.4 VDD_1V8 V
POWER SUPPLY
IAVDD_5V Supply current from AVDD_5V At 20MSPS throughput (ADS9219) 38.2 50 mA
At 10MSPS throughput (ADS9218) 31.2 40
At 5MSPS throughput (ADS9217) 18.5 24
Power-down 2
IVDD_1V8 Supply current from VDD_1V8 At 20MSPS throughput (ADS9219) 85.3 97 mA
At 10MSPS throughput (ADS9218) 69.8 89
At 5MSPS throughput (ADS9217) 48.8 66

Power-down

 2
(1) These specifications include full temperature range variation but not the error contribution from internal reference.