SBASA74A January   2023  – April 2024 ADS9218 , ADS9219

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Thermal Information
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9219
    11. 5.11 Typical Characteristics
    12. 5.12 Typical Characteristics: ADS9217
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 Fixed Pattern
          2. 6.3.8.3.2 Alternating Test Pattern
          3. 6.3.8.3.3 Digital Ramp
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.7 Digital Down Converter

The ADS921x includes an optional on-chip digital down conversion (DDC) that is enabled by SPI register settings. As shown in Figure 6-5, the DDC includes a digital mixer and a 24-bit, numerically controlled oscillator (NCO). The digital mixer generates 24-bit I and Q outputs that represent complex mixing of ADC output data with the NCO output frequency. Each channel of the ADC generates a 48-bit output corresponding to the 24-bit I and Q outputs, respectively, from the digital mixer.

GUID-20240411-SS0I-NWDF-XQSN-VVSWDVNXJ1FN-low.svg Figure 6-5 Data Path When Using a Digital Down Converter

The NCO is common for both ADC A and ADC B. The output frequency of the NCO, given by Equation 2, is configured using the NCO_FREQUENCY register (address 0xFD and 0xFE).

Equation 2. f N C O = f S M P L _ C L K 2 24 × N C O _ F R E Q U E N C Y 23 : 0   &   0 x F F F F F 0   H z

The output phase of the NCO is reset by applying a pulse on the SMPL_SYNC pin as shown in Figure 5-7. As shown in Equation 3 and Table 6-4, the initial phase of the NCO output is configured using the NCO_PHASE register (address 0xFC and 0xFD).

Equation 3. N C O _ P H A S E 23 : 0 = I n i t i a l   p h a s e 2 π × 2 24 &   0 x F F F F F 0
Table 6-4 Initial NCO Phase
NCO_PHASE[23:0] INITIAL PHASE
0x000000 0
0x7FFFF0 π
0xFFFFF0 2π

Use a decimation factor of either 2, 4, 8, or 16 with the DDC. Table 6-5 shows the register configuration for decimating the DDC output.

Table 6-5 Decimation Settings for the DDC
DECIMATION REGISTER VALUE
2 OSR_EN (0x0D[6]) 1
OSR (0x0D[5:2] 0
OSR_CLK (0xC0[9:7]) 0
Common settings for decimation factors 4, 8, and 16 CLK3 (0xC5[9]) 1
OSR_INIT1 (0xC0[11:10]) 1
OSR_INIT2 (0xC4[5:4]) 2
OSR_INIT3 (0xC4[1]) 1
OSR_EN (0x0D[6]) 1
4 OSR (0x0D[5:2] 1
OSR_CLK (0xC0[9:7]) 0
8 OSR (0x0D[5:2] 2
OSR_CLK (0xC0[9:7]) 4
16 OSR (0x0D[5:2] 3
OSR_CLK (0xC0[9:7]) 5