SLASF77A December   2022  – September 2023 AFE11612-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Characteristics
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Internal Reference
    11. 6.11 Typical Characteristics: Temperature Sensor
    12. 6.12 Typical Characteristics: Digital Inputs
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Primary ADC Operation
        1. 7.3.1.1 Analog Inputs
          1. 7.3.1.1.1 Single-Ended Analog Input
          2. 7.3.1.1.2 Fully Differential Input
        2. 7.3.1.2 ADC Trigger Signals (See AFE configuration register 0 )
        3. 7.3.1.3 Double-Buffered ADC Data Registers
          1. 7.3.1.3.1 ADC Data Format
        4. 7.3.1.4 SCLK Clock Noise Reduction
        5. 7.3.1.5 Data Available Pin (DAV)
        6. 7.3.1.6 Convert Pin (CNVT)
        7. 7.3.1.7 Analog Input Out-of-Range Detection (See The Analog Input Out-of-Range Alarm Section)
        8. 7.3.1.8 Full-Scale Range of the Analog Input
      2. 7.3.2 Secondary ADC and Temperature Sensor Operation
        1. 7.3.2.1 Remote Sensing Diode
        2. 7.3.2.2 Ideality Factor
        3. 7.3.2.3 Filtering
        4. 7.3.2.4 Series Resistance Cancellation
        5. 7.3.2.5 Reading Temperature Data
        6. 7.3.2.6 Conversion Time
      3. 7.3.3 Reference Operation
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
      4. 7.3.4 DAC Operation
        1. 7.3.4.1 Resistor String
        2. 7.3.4.2 DAC Output
          1. 7.3.4.2.1 Full-Scale Output Range
          2. 7.3.4.2.2 DAC Output After Power-On Reset
        3. 7.3.4.3 Double-Buffered DAC Data Registers
        4. 7.3.4.4 Load DAC Latch
        5. 7.3.4.5 Synchronous Output Updating
        6. 7.3.4.6 Clear DACs
        7. 7.3.4.7 DAC Output Thermal Protection
      5. 7.3.5 Alarm Operation
        1. 7.3.5.1 Analog Input Out-of-Range Alarm
        2. 7.3.5.2 ALARM Pin
        3. 7.3.5.3 Hysteresis
        4. 7.3.5.4 False-Alarm Protection
      6. 7.3.6 General-Purpose Input and Output Pins (GPIO-0 To GPIO-7)
      7. 7.3.7 Device Reset Options
        1. 7.3.7.1 Hardware Reset
        2. 7.3.7.2 Software Reset
        3. 7.3.7.3 Power-On Reset (POR)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Output Mode
      2. 7.4.2 ADC Conversion Modes
        1. 7.4.2.1 Programmable Conversion Rate
        2. 7.4.2.2 Handshaking with the Host (See AFE configuration register 0 )
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 F/S-Mode Protocol
        2. 7.5.1.2 Hs-Mode Protocol
        3. 7.5.1.3 Address Pointer
        4. 7.5.1.4 Timeout Function
        5. 7.5.1.5 Device Communication Protocol For I2C
          1. 7.5.1.5.1 Writing A Single Register ( )
          2. 7.5.1.5.2 Writing Multiple Registers ( )
          3. 7.5.1.5.3 Reading a Single Register ( )
          4. 7.5.1.5.4 Reading Multiple Registers ( and )
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Shift Register
        2. 7.5.2.2 SPI Communications Command
        3. 7.5.2.3 Standalone Operation
        4. 7.5.2.4 Daisy-Chain Operation
    6. 7.6 Register Maps
      1. 7.6.1  Temperature Data Registers (Read-Only)
        1. 7.6.1.1 LT-Temperature-Data (LT_TEMP) Register (address = 00h) [reset = 0000h, 0°C]
        2. 7.6.1.2 D1-Temperature-Data (D1_TEMP) Register (address = 01h) [reset = 0000h, 0°C]
        3. 7.6.1.3 D2-Temperature-Data (D2_TEMP) Register (address = 02h) [reset = 0000h, 0°C]
      2. 7.6.2  Temperature Configuration (TEMP_CONFIG) Register (address = 0Ah) [reset = 003Ch or 3CFFh]
      3. 7.6.3  Temperature Conversion Rate (TEMP_CONV_RATE) Register (address = 0Bh) [reset = 0007h or 07FFh]
      4. 7.6.4  η-Factor Correction Registers: D1_N_ADJUST and D2_N_ADJUST (address = 21h and 22h) [reset = 0000h or 00FFh]
      5. 7.6.5  ADC-n-Data (ADC_n) Registers (addresses = 23h to 32h) [reset = 0000h]
      6. 7.6.6  DAC-n-Data (DAC_n) Registers (addresses = 33h to 3Eh) [reset = 0000h)
      7. 7.6.7  DAC-n-CLR-Setting (DAC_n_CLR) Registers (addresses = 3Fh to 4Ah) [reset = 0000h]
      8. 7.6.8  GPIO Register (address = 4Bh) [reset = 00FFh]
      9. 7.6.9  AFE Configuration Register 0 (AFE_CONFIG_0) (address = 4Ch) [reset = 2000h]
      10. 7.6.10 AFE Configuration Register 1 (AFE_CONFIG_1) (Address = 4Dh) [reset = 0070h]
      11. 7.6.11 Alarm Control Register (ALR_CTRL) (address = 4Eh) [reset = 0000h]
      12. 7.6.12 STATUS Register (Address = 4Fh) [reset = 0000h]
      13. 7.6.13 ADC Channel Register 0 (ADC_CH0) (address = 50h) [reset = 0000h]
      14. 7.6.14 ADC Channel Register 1 (ADC_CH1) (address = 51h) [reset = 0000h]
      15. 7.6.15 ADC Gain Register (ADC_GAIN) (address = 52h) [reset = FFFFh]
      16. 7.6.16 AUTO_DAC_CLR_SOURCE Register (address = 53h) [reset = 0004h]
      17. 7.6.17 AUTO_DAC_CLR_EN Register (address = 54h) [reset = 0000h]
      18. 7.6.18 SW_DAC_CLR Register (address = 55h) [reset = 0000h]
      19. 7.6.19 HW_DAC_CLR_EN_0 Register (address = 56h) [reset = 0000h]
      20. 7.6.20 HW_DAC_CLR_EN_1 Register (address = 57h) [reset = 0000h]
      21. 7.6.21 DAC Configuration (DAC_CONFIG) Register (address = 58h) [reset = 0000h]
      22. 7.6.22 DAC Gain (DAC_GAIN) Register (address = 59h) [reset = 0000h]
      23. 7.6.23 Analog Input Channel Threshold Registers (addresses = 5Ah To 61h)
        1. 7.6.23.1 Input-n-High-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Ah, 1 = 5Ch, 2 = 5Eh, 3 = 60h) [reset = 0FFFh]
        2. 7.6.23.2 Input-n-Low-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Bh, 1 = 5Dh, 2 = 5Fh, 3 = 61h) (reset = 0000h)
      24. 7.6.24 Temperature Threshold Registers
        1. 7.6.24.1 LT_HIGH_THRESHOLD Register (address = 62h) [reset = 07FFh, +255.875°C]
        2. 7.6.24.2 LT_LOW_THRESHOLD Register (address = 63h) [reset = 0800h, –256°C]
        3. 7.6.24.3 D1_HIGH_THRESHOLD Register (address = 64h) [reset = 07FFh, +255.875°C]
        4. 7.6.24.4 D1_LOW_THRESHOLD Register (address = 65h) [reset = 0800h, –256°C]
        5. 7.6.24.5 D2_HIGH_THRESHOLD Register (address = 66h) [reset = 07FFh, +255.875°C]
        6. 7.6.24.6 D2_LOW_THRESHOLD Register (address = 67h) [reset = 0800h, –256°C]
      25. 7.6.25 Hysteresis Registers
        1. 7.6.25.1 Hysteresis Register 0 (HYST_0) (address = 68h) [reset = 0810h, 8 LSB]
        2. 7.6.25.2 Hysteresis Register 1 (HYST_1) (address = 69h) [reset = 0810h, 8 LSB]
        3. 7.6.25.3 Hysteresis Register 2 (HYST_2) (address = 6Ah) [reset = 2108h, 8°C]
      26. 7.6.26 Power-Down Register (PWR_DOWN) (address = 6Bh) [reset = 0000h)
      27. 7.6.27 Device ID Register (DEVICE_ID) (read only address = 6Ch) [reset = 1220h]
      28. 7.6.28 Software Reset (SW_RST) Register (read or write address = 7Ch) [reset = N/A)
        1. 7.6.28.1 SPI Mode
        2. 7.6.28.2 I2C Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sequencing
        2. 8.2.2.2 Negative GaN Biasing
        3. 8.2.2.3 VDRAIN Monitoring
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Diagram
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Maps

The device has several 16-bit registers that consist of a high byte (8 MSBs) and a low byte (8 LSBs). An 8-bit register pointer points to the proper register. The pointer does not change after an operation. Table 7-10 lists the registers for the device. The default values are for SPI operation; see the following subsections for I2C default values.

Table 7-10 Register Map
ADDR (HEX) REGISTER TYPE RESET (HEX) BIT DESCRIPTION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 LT_
TEMP		 R 0000 LT_DATA [11:0] Reserved
01 D1_
TEMP		 R 0000 D1_DATA [11:0] Reserved
02 D2_
TEMP		 R 0000 D2_DATA [11:0] Reserved
0A TEMP_
CONFIG		 R/W 003C Reserved D2EN D1EN LTEN RC Reserved
0B TEMP_
CONV_
RATE		 R/W 0007 Reserved RATE[2:0]
21 D1_N_
ADJUST		 R/W 0000 Reserved N_ADJUST[7:0]
22 D2_N_
ADJUST		 R/W 0000 Reserved N_ADJUST[7:0]
23 ADC_0 R 0000 Reserved ADC[11:0]
24 ADC_1 R 0000 Reserved ADC[11:0]
25 ADC_2 R 0000 Reserved ADC[11:0]
26 ADC_3 R 0000 Reserved ADC[11:0]
27 ADC_4 R 0000 Reserved ADC[11:0]
28 ADC_5 R 0000 Reserved ADC[11:0]
29 ADC_6 R 0000 Reserved ADC[11:0]
2A ADC_7 R 0000 Reserved ADC[11:0]
2B ADC_8 R 0000 Reserved ADC[11:0]
2C ADC_9 R 0000 Reserved ADC[11:0]
2D ADC_10 R 0000 Reserved ADC[11:0]
2E ADC_11 R 0000 Reserved ADC[11:0]
2F ADC_12 R 0000 Reserved ADC[11:0]
30 ADC_13 R 0000 Reserved ADC[11:0]
31 ADC_14 R 0000 Reserved ADC[11:0]
32 ADC_15 R 0000 Reserved ADC[11:0]
33 DAC_0 R/W 0000 Reserved DAC[11:0]
34 DAC_1 R/W 0000 Reserved DAC[11:0]
35 DAC_2 R/W 0000 Reserved DAC[11:0]
36 DAC_3 R/W 0000 Reserved DAC[11:0]
37 DAC_4 R/W 0000 Reserved DAC[11:0]
38 DAC_5 R/W 0000 Reserved DAC[11:0]
39 DAC_6 R/W 0000 Reserved DAC[11:0]
3A DAC_7 R/W 0000 Reserved DAC[11:0]
3B DAC_8 R/W 0000 Reserved DAC[11:0]
3C DAC_9 R/W 0000 Reserved DAC[11:0]
3D DAC_10 R/W 0000 Reserved DAC[11:0]
3E DAC_11 R/W 0000 Reserved DAC[11:0]
3F DAC_0_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
40 DAC_1_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
41 DAC_2_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
42 DAC_3_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
43 DAC_4_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
44 DAC_5_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
45 DAC_6_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
46 DAC_7_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
47 DAC_8_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
48 DAC_9_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
49 DAC_10_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
4A DAC_11_
CLR		 R/W 0000 Reserved DAC_CLR[11:0]
4B GPIO R/W 00FF Reserved GPIO[7:0]
4C AFE_
CONFIG_0		 R/W 2000 Reserved CMODE ICONV ILDAC ADC_
REF_
INT		 EN_
ALARM		 Reserved DAVF GALR Reserved
4D AFE_
CONFIG_1		 R/W 0070 Reserved CONV_
RATE_1		 CONV_
RATE_0		 CH_
FALR_
CT_2		 CH_
FALR_
CT_1		 CH_
FALR_
CT_0		 TEMP_
FALR_
CT_1		 TEMP_
FALR_
CT_0		 Reserved
4E ALR_CTRL R/W 0000 Reserved EALR_
CH0		 EALR_
CH1		 EALR_
CH2		 EALR_
CH3		 EALR_
LT_
LOW		 EALR_
LT_
HIGH		 EALR_
D1_
LOW		 EALR_
D1_
HIGH		 EALR_
D2_
LOW		 EALR_
D2_
HIGH		 EALR_
D1_
FAIL		 EALR_
D2_
FAIL		 ALARM_
LATCH_
DIS		 Reserved
4F STATUS R 0000 Reserved CH0_
ALR		 CH1_
ALR		 CH2_
ALR		 CH3_
ALR		 LT_
LOW_
ALR		 LT_
HIGH_
ALR		 D1_
LOW_
ALR		 D1_
HIGH_
ALR		 D2_
LOW_
ALR		 D2_
HIGH_
ALR		 D1_
FAIL_
ALR		 D2_
FAIL_
ALR		 THERM_
ALR		 Reserved
50 ADC_CH0 R/W 0000 Reserved SE0 SE1 DF
(CH0+,
CH1-)		 SE2 SE3 DF
(CH2+,
CH3-)		 SE4 SE5 SE6 SE7 SE8 SE9 SE10 SE11 SE12
51 ADC_CH1 R/W 0000 Reserved SE13 SE14 SE15 Reserved
52 ADC_GAIN R/W FFFF ADG0 ADG1 ADG2 ADG3 ADG4 ADG5 ADG6 ADG7 ADG8 ADG9 ADG10 ADG11 ADG12 ADG13 ADG14 ADG15
53 AUTO_DAC_
CLR_
SOURCE		 R/W 0004 Reserved CH0_
ALR_
CLR		 CH1_
ALR		 CH2_
ALR_
CLR		 CH3_
ALR_
CLR		 LT_
LOW_
ALR_
CLR		 LT_
HIGH_
ALR_
CLR		 D1_
LOW_
ALR_
CLR		 D1_
HIGH_
ALR_
CLR		 D2_
LOW_
ALR_
CLR		 D2_
HIGH_
ALR_
CLR		 D1_
FAIL_
ALR_
CLR		 D2_
FAIL_
ALR_
CLR		 THERM_
ALR_
CLR		 Reserved
54 AUTO_DAC_
CLR_EN		 R/W 0000 Reserved ACLR[11:0] Reserved
55 SW_DAC_
CLR		 R/W 0000 Reserved ICLR[11:0] Reserved
56 HW_DAC_
CLR_EN_0		 R/W 0000 Reserved H0CLR[11:0] Reserved
57 HW_DAC_
CLR_EN_1		 R/W 0000 Reserved H1CLR[11:0] Reserved
58 DAC_CONFIG R/W 0000 Reserved SLDA[11:0]
59 DAC_GAIN R/W 0000 Reserved DAC_GAIN[11:0]
5A IN_0_
HIGH_
THRESHOLD		 R/W 0FFF Reserved THRH[11:0]
5B IN_0_
LOW_
THRESHOLD		 R/W 0000 Reserved THRL[11:0]
5C IN_1_
HIGH_
THRESHOLD		 R/W 0FFF Reserved THRH[11:0]
5D IN_1_
LOW_
THRESHOLD		 R/W 0000 Reserved THRL[11:0]
5E IN_2_
HIGH_
THRESHOLD		 R/W 0FFF Reserved THRH[11:0]
5F IN_2_
LOW_
THRESHOLD		 R/W 0000 Reserved THRL[11:0]
60 IN_3_
HIGH_
THRESHOLD		 R/W 0FFF Reserved THRH[11:0]
61 IN_3_
LOW_
THRESHOLD		 R/W 0000 Reserved THRL[11:0]
62 LT_
HIGH_
THRESHOLD		 R/W 07FF Reserved THRH[11:0]
63 LT_
LOW_
THRESHOLD		 R/W 0800 Reserved THRL[11:0]
64 D1_
HIGH_
THRESHOLD		 R/W 07FF Reserved THRH[11:0]
65 D1_
LOW_
THRESHOLD		 R/W 0800 Reserved THRL[11:0]
66 D2_
HIGH_
THRESHOLD		 R/W 07FF Reserved THRH[11:0]
67 D2_
LOW_
THRESHOLD		 R/W 0800 Reserved THRL[11:0]
68 HYST_0 R/W 0810 Reserved CH0_HYS [6:0] CH1_HYS [6:0] Reserved
69 HYST_1 R/W 0810 Reserved CH2_HYS [6:0] CH3_HYS [6:0] Reserved
6A HYST_2 R/W 2108 Reserved D2_
HYS_7		 D2_
HYS_6		 D2_
HYS_5		 D2_
HYS_4		 D2_
HYS_3		 D1_
HYS_7		 D1_
HYS_6		 D1_
HYS_5		 D1_
HYS_4		 D1_
HYS_3		 LT_
HYS_7		 LT_
HYS_6		 LT_
HYS_5		 LT_
HYS_4		 LT_
HYS_3
6B PWR_DOWN R/W 0000 Reserved PADC PREF PDAC0 PDAC1 PDAC2 PDAC3 PDAC4 PDAC5 PDAC6 PDAC7 PDAC8 PDAC9 PDAC10 PDAC11 Reserved
6C DEVICE_ID R 1220 DEVICE_ID[15:0]
7C SW_RST R/W N/A SW_RST[15:0]
Note: A few registers have different reset values when using SPI and I2C respectively; for these registers, the table lists the SPI reset value (register descriptions contain separate I2C reset values wherever applicable).