SLASF77A December   2022  – September 2023 AFE11612-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Characteristics
    7. 6.7  Timing Diagrams
    8. 6.8  Typical Characteristics: DAC
    9. 6.9  Typical Characteristics: ADC
    10. 6.10 Typical Characteristics: Internal Reference
    11. 6.11 Typical Characteristics: Temperature Sensor
    12. 6.12 Typical Characteristics: Digital Inputs
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Primary ADC Operation
        1. 7.3.1.1 Analog Inputs
          1. 7.3.1.1.1 Single-Ended Analog Input
          2. 7.3.1.1.2 Fully Differential Input
        2. 7.3.1.2 ADC Trigger Signals (See AFE configuration register 0 )
        3. 7.3.1.3 Double-Buffered ADC Data Registers
          1. 7.3.1.3.1 ADC Data Format
        4. 7.3.1.4 SCLK Clock Noise Reduction
        5. 7.3.1.5 Data Available Pin (DAV)
        6. 7.3.1.6 Convert Pin (CNVT)
        7. 7.3.1.7 Analog Input Out-of-Range Detection (See The Analog Input Out-of-Range Alarm Section)
        8. 7.3.1.8 Full-Scale Range of the Analog Input
      2. 7.3.2 Secondary ADC and Temperature Sensor Operation
        1. 7.3.2.1 Remote Sensing Diode
        2. 7.3.2.2 Ideality Factor
        3. 7.3.2.3 Filtering
        4. 7.3.2.4 Series Resistance Cancellation
        5. 7.3.2.5 Reading Temperature Data
        6. 7.3.2.6 Conversion Time
      3. 7.3.3 Reference Operation
        1. 7.3.3.1 Internal Reference
        2. 7.3.3.2 External Reference
      4. 7.3.4 DAC Operation
        1. 7.3.4.1 Resistor String
        2. 7.3.4.2 DAC Output
          1. 7.3.4.2.1 Full-Scale Output Range
          2. 7.3.4.2.2 DAC Output After Power-On Reset
        3. 7.3.4.3 Double-Buffered DAC Data Registers
        4. 7.3.4.4 Load DAC Latch
        5. 7.3.4.5 Synchronous Output Updating
        6. 7.3.4.6 Clear DACs
        7. 7.3.4.7 DAC Output Thermal Protection
      5. 7.3.5 Alarm Operation
        1. 7.3.5.1 Analog Input Out-of-Range Alarm
        2. 7.3.5.2 ALARM Pin
        3. 7.3.5.3 Hysteresis
        4. 7.3.5.4 False-Alarm Protection
      6. 7.3.6 General-Purpose Input and Output Pins (GPIO-0 To GPIO-7)
      7. 7.3.7 Device Reset Options
        1. 7.3.7.1 Hardware Reset
        2. 7.3.7.2 Software Reset
        3. 7.3.7.3 Power-On Reset (POR)
    4. 7.4 Device Functional Modes
      1. 7.4.1 DAC Output Mode
      2. 7.4.2 ADC Conversion Modes
        1. 7.4.2.1 Programmable Conversion Rate
        2. 7.4.2.2 Handshaking with the Host (See AFE configuration register 0 )
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 F/S-Mode Protocol
        2. 7.5.1.2 Hs-Mode Protocol
        3. 7.5.1.3 Address Pointer
        4. 7.5.1.4 Timeout Function
        5. 7.5.1.5 Device Communication Protocol For I2C
          1. 7.5.1.5.1 Writing A Single Register ( )
          2. 7.5.1.5.2 Writing Multiple Registers ( )
          3. 7.5.1.5.3 Reading a Single Register ( )
          4. 7.5.1.5.4 Reading Multiple Registers ( and )
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 SPI Shift Register
        2. 7.5.2.2 SPI Communications Command
        3. 7.5.2.3 Standalone Operation
        4. 7.5.2.4 Daisy-Chain Operation
    6. 7.6 Register Maps
      1. 7.6.1  Temperature Data Registers (Read-Only)
        1. 7.6.1.1 LT-Temperature-Data (LT_TEMP) Register (address = 00h) [reset = 0000h, 0°C]
        2. 7.6.1.2 D1-Temperature-Data (D1_TEMP) Register (address = 01h) [reset = 0000h, 0°C]
        3. 7.6.1.3 D2-Temperature-Data (D2_TEMP) Register (address = 02h) [reset = 0000h, 0°C]
      2. 7.6.2  Temperature Configuration (TEMP_CONFIG) Register (address = 0Ah) [reset = 003Ch or 3CFFh]
      3. 7.6.3  Temperature Conversion Rate (TEMP_CONV_RATE) Register (address = 0Bh) [reset = 0007h or 07FFh]
      4. 7.6.4  η-Factor Correction Registers: D1_N_ADJUST and D2_N_ADJUST (address = 21h and 22h) [reset = 0000h or 00FFh]
      5. 7.6.5  ADC-n-Data (ADC_n) Registers (addresses = 23h to 32h) [reset = 0000h]
      6. 7.6.6  DAC-n-Data (DAC_n) Registers (addresses = 33h to 3Eh) [reset = 0000h)
      7. 7.6.7  DAC-n-CLR-Setting (DAC_n_CLR) Registers (addresses = 3Fh to 4Ah) [reset = 0000h]
      8. 7.6.8  GPIO Register (address = 4Bh) [reset = 00FFh]
      9. 7.6.9  AFE Configuration Register 0 (AFE_CONFIG_0) (address = 4Ch) [reset = 2000h]
      10. 7.6.10 AFE Configuration Register 1 (AFE_CONFIG_1) (Address = 4Dh) [reset = 0070h]
      11. 7.6.11 Alarm Control Register (ALR_CTRL) (address = 4Eh) [reset = 0000h]
      12. 7.6.12 STATUS Register (Address = 4Fh) [reset = 0000h]
      13. 7.6.13 ADC Channel Register 0 (ADC_CH0) (address = 50h) [reset = 0000h]
      14. 7.6.14 ADC Channel Register 1 (ADC_CH1) (address = 51h) [reset = 0000h]
      15. 7.6.15 ADC Gain Register (ADC_GAIN) (address = 52h) [reset = FFFFh]
      16. 7.6.16 AUTO_DAC_CLR_SOURCE Register (address = 53h) [reset = 0004h]
      17. 7.6.17 AUTO_DAC_CLR_EN Register (address = 54h) [reset = 0000h]
      18. 7.6.18 SW_DAC_CLR Register (address = 55h) [reset = 0000h]
      19. 7.6.19 HW_DAC_CLR_EN_0 Register (address = 56h) [reset = 0000h]
      20. 7.6.20 HW_DAC_CLR_EN_1 Register (address = 57h) [reset = 0000h]
      21. 7.6.21 DAC Configuration (DAC_CONFIG) Register (address = 58h) [reset = 0000h]
      22. 7.6.22 DAC Gain (DAC_GAIN) Register (address = 59h) [reset = 0000h]
      23. 7.6.23 Analog Input Channel Threshold Registers (addresses = 5Ah To 61h)
        1. 7.6.23.1 Input-n-High-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Ah, 1 = 5Ch, 2 = 5Eh, 3 = 60h) [reset = 0FFFh]
        2. 7.6.23.2 Input-n-Low-Threshold Register (where n = 0, 1, 2, 3; addresses: 0 = 5Bh, 1 = 5Dh, 2 = 5Fh, 3 = 61h) (reset = 0000h)
      24. 7.6.24 Temperature Threshold Registers
        1. 7.6.24.1 LT_HIGH_THRESHOLD Register (address = 62h) [reset = 07FFh, +255.875°C]
        2. 7.6.24.2 LT_LOW_THRESHOLD Register (address = 63h) [reset = 0800h, –256°C]
        3. 7.6.24.3 D1_HIGH_THRESHOLD Register (address = 64h) [reset = 07FFh, +255.875°C]
        4. 7.6.24.4 D1_LOW_THRESHOLD Register (address = 65h) [reset = 0800h, –256°C]
        5. 7.6.24.5 D2_HIGH_THRESHOLD Register (address = 66h) [reset = 07FFh, +255.875°C]
        6. 7.6.24.6 D2_LOW_THRESHOLD Register (address = 67h) [reset = 0800h, –256°C]
      25. 7.6.25 Hysteresis Registers
        1. 7.6.25.1 Hysteresis Register 0 (HYST_0) (address = 68h) [reset = 0810h, 8 LSB]
        2. 7.6.25.2 Hysteresis Register 1 (HYST_1) (address = 69h) [reset = 0810h, 8 LSB]
        3. 7.6.25.3 Hysteresis Register 2 (HYST_2) (address = 6Ah) [reset = 2108h, 8°C]
      26. 7.6.26 Power-Down Register (PWR_DOWN) (address = 6Bh) [reset = 0000h)
      27. 7.6.27 Device ID Register (DEVICE_ID) (read only address = 6Ch) [reset = 1220h]
      28. 7.6.28 Software Reset (SW_RST) Register (read or write address = 7Ch) [reset = N/A)
        1. 7.6.28.1 SPI Mode
        2. 7.6.28.2 I2C Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Sequencing
        2. 8.2.2.2 Negative GaN Biasing
        3. 8.2.2.3 VDRAIN Monitoring
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Diagram
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

all minimum and maximum specifications at TA = –55℃ to +125℃, all typical specifications at TA = 25℃, AVCC = 5.5 V, AVDD = DVDD = 4.5 V to 5.5 V, IOVDD = 2.7 V to 5.5 V, internal reference, and DAC outputs unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DAC CHARACTERISTICS(1)
Resolution 12 Bits
Full-scale output voltage VREF = 2.5 V 0 5 V
DNL Differential nonlinearity Specified 12-bit monotonic –1 1 LSB
INL Integral nonlinearity –1.25 1.25 LSB
TUE Total unadjusted error TA = 25°C –10 10 mV
Offset error TA = 25°C –2 2 mV
Offset error temperature drift ±1 ppm/°C
Gain error External 2.5-V reference –0.15 0.15 %FSR
Gain error temperature drift ±2 ppm/°C
Load current(2) Source within 200 mV of supply 10 mA
Sink within 300 mV of supply –10 mA
Short-circuit current(2) ±30 mA
Capacitive load stability(3) 0 10 nF
DC output impedance(3) Midscale code 0.3 Ω
Output voltage settling time RL = 2 kΩ, CL = 200 pF, 1/4 to 3/4 scale settling to 1/2 LSB 3 µs
Slew rate 1/4 to 3/4 scale transition, 10% to 90% 1.5 V/µs
Output noise f = 0.1 Hz to 10 Hz, midscale code 8 µVpp
Output noise density f = 1 kHz, midscale code, external reference 81 nV/√Hz
Code change glitch impulse 1 LSB change around major carrier 0.15 nV-s
Supply ramp-up glitch amplitude AVCC = 0-V to 5-V, 2-ms ramp 5 mV
Digital feedthrough Device is not accessed 0.15 nV-s
ADC CHARACTERISTICS
Resolution 12 Bits
Full-scale input voltage Single-ended, 0 V to VREF 0 VREF V
Single-ended, 0 V to 2 × VREF 0  2 × VREF
Fully differential, VIN+ – VIN–,
0 V to VREF		 –VREF VREF
Fully differential, VIN+ – VIN–,
0 V to 2 × VREF		 –2 × VREF 2 × VREF
Absolute input voltage GND – 0.2 AVDD + 0.2 V
DNL Differential nonlinearity Specified 12-bit monotonic –1 1 LSB
INL Integral nonlinearity –1 1 LSB
Offset error –3 3 LSB
Offset error match ±0.4 LSB
Gain error Single-ended mode,
external 2.5-V reference		 –5 5 LSB
Differential mode, 0 V to VREF,
VCM = 1.25 V, external 2.5-V reference		 –5 5
Differential mode, 0 V to 2 × VREF,
VCM = 2.5 V,  external 2.5-V reference		 –5 5
Gain error match Single-ended mode ±0.4 LSB
Differential mode ±0.5
Zero code error Differential mode, 0 V to VREF,
VCM = 1.25 V, external 2.5-V reference		 –3 3 LSB
Differential mode, 0 V to 2 × VREF,
VCM = 2.5 V, external 2.5-V reference		 –3 3
Zero code error match ±0.5 LSB
Common-mode rejection Differential mode, 0 V to 2 × VREF,
measured at dc		 67 dB
Input capacitance 0 V to VREF 118 pF
0 V to 2 × VREF 73
Input bias current Unselected ADC input ±10 µA
Conversion rate External single analog channel,
auto-mode conversion		 500 kSPS
External single analog channel,
direct-mode conversion		 167
Conversion time External single analog channel 2 µs
Autocycle update rate All 16 single-ended inputs enabled 32 µs
Throughput rate SCLK ≥ 12 MHz, external single-channel 500 kSPS
INTERNAL TEMPERATURE SENSOR CHARACTERISTICS
Accuracy AVDD = 5 V, TA = –55°C to +125°C –4.5 4.5 °C
AVDD = 5 V, TA = 0°C to 100°C –1.5 1.5
Resolution 0.125 °C
Conversion rate Remote temperature sensors disabled 15 ms
REMOTE TEMPERATURE SENSOR CHARACTERISTICS 
Accuracy(4) AVDD = 5 V, TA = –55°C to +125°C,
TD = –40°C to +150°C		 –6 6 °C
AVDD = 5 V, TA = 0°C to +100°C,
TD = –40°C to +150°C		 –1.5 1.5
Resolution 0.125 °C
Conversion rate per sensor With resistance cancellation (RC = 1) 93 ms
Without resistance cancellation (RC = 0) 44
INTERNAL REFERENCE CHARACTERISTICS
VREF-OUT Internal reference voltage TA = 25°C, REF-OUT pin 2.48 2.5 2.52 V
Internal reference temperature coefficient TA = –55°C to +125°C 25 ppm/°C
Internal reference impedance 0.4 Ω
Internal reference output noise f = 0.1 Hz to 10 Hz 13 µVPP
Internal reference noise density f = 1 kHz 260 nV/√Hz
Internal reference load current ±5 mA
EXTERNAL REFERENCE CHARACTERISTICS
VREF Input voltage DAC reference input, REF-DAC pin 1.4 2.5 2.6 V
ADC reference input, ADC-REF-IN pin 1.4 2.5 2.6
Input current DAC reference input, VREF = 2.5 V 170 µA
ADC reference input, VREF = 2.5 V 145
ADC reference buffer offset TA = 25°C –5 5 mV
DIGITAL INPUT CHARACTERISTICS
VIH High-level input voltage IOVDD = 5 V 2.1 V
IOVDD = 3.3 V 2.2
VIL Low-level input voltage IOVDD = 5 V 0.8 V
IOVDD = 3.3 V 0.7
Input current All except SCL, SDA, ALARM and GPIO –1 1 µA
SCL, SDA, ALARM and GPIO –5 5
Input pin capacitance 5 pF
DIGITAL OUTPUT CHARACTERISTICS
VOH High-level output voltage IOVDD = 5 V, ISOURCE = 3 mA 4.8 V
IOVDD = 3.3 V, ISOURCE = 3 mA 2.9
VOL Low-level output voltage ISINK = 3 mA 0.4 V
VOL Open-drain low-level output voltage GPIO and ALARM, IOVDD = 5 V,
ISINK = 5 mA		 0.4 V
GPIO and ALARM, IOVDD = 3.3 V,
ISINK = 2 mA		 0.4
SDA and SCL, IOVDD = 5 V,
ISINK = 3 mA		 0.4
SDA and SCL, IOVDD = 3.3 V,
ISINK = 3 mA		 0.4
High-impedance leakage –5 5 µA
Output pin capacitance 10 pF
POWER CONSUMPTION CHARACTERISTICS
IVDD AVDD and DVDD supply current AVDD and DVDD combined, no DAC load, DACs at midscale code and ADC at the fastest autoconversion rate 8 19 mA
AVDD and DVDD combined, power-down mode 1.6
IAVCC AVCC supply current No DAC load, DACs at midscale code and ADC at the fastest autoconversion rate 7 mA
Power consumption No DAC load, DACs at midscale code and ADC at the fastest autoconversion rate, AVDD = DVDD = 5 V, AVCC = 5 V 95 120 mW
(1) End point fit between codes 32 to 4095.
(2) Overload condition protection. Junction temperature can be exceeded during current limit. Operation greater than the specified maximum junction temperature can impair device reliability.
(3) Specified by design and characterization. Not tested during production.
(4) TD is the external diode temperature.