SLASF77A December 2022 – September 2023 AFE11612-SEP
PRODUCTION DATA
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
I2C STANDARD MODE TIMING REQUIREMENTS | |||||
f(SCL)(1) | I2C clock frequency | 0 | 100 | kHz | |
t(LOW) | SCL clock low period | 4.7 | µs | ||
t(HIGH) | SCL clock high period | 4.0 | µs | ||
t(SUSTA) | Repeated start condition setup time | 4.7 | µs | ||
t(HDSTA) | Hold time after repeated start condition. After this period, the first clock is generated |
4.0 | µs | ||
t(SUSTO) | Stop condition setup time | 4.0 | µs | ||
t(BUF) | Bus free time between stop and start condition | 4.7 | µs | ||
t(SUDAT) | Data setup time | 250 | ns | ||
t(HDDAT) | Data hold time | 0 | 3.45 | µs | |
tR,SCL | Clock rise time | 1000 | ns | ||
tF,SCL | Clock fall time | 300 | ns | ||
tR,SDA | Data rise time | 1000 | ns | ||
tF,SDA | Data fall time | 300 | ns | ||
CB | Capacitive load for each bus line | 400 | pF | ||
I2C FAST MODE TIMING REQUIREMENTS | |||||
f(SCL)(1) | I2C clock frequency | 0 | 400 | kHz | |
t(LOW) | SCL clock low period | 1.3 | µs | ||
t(HIGH) | SCL clock high period | 0.6 | µs | ||
t(SUSTA) | Repeated start condition setup time | 0.6 | µs | ||
t(HDSTA) | Hold time after repeated start condition. After this period, the first clock is generated |
0.6 | µs | ||
t(SUSTO) | Stop condition setup time | 0.6 | µs | ||
t(BUF) | Bus free time between stop and start condition | 1.3 | µs | ||
t(SUDAT) | Data setup time | 100 | ns | ||
t(HDDAT) | Data hold time | 0 | 0.9 | µs | |
tR,SCL | Clock rise time | 20 + 0.1 CB | 300 | ns | |
tF,SCL | Clock fall time | 20 + 0.1 CB | 300 | ns | |
tR,SDA | Data rise time | 20 + 0.1 CB | 300 | ns | |
tF,SDA | Data fall time | 20 + 0.1 CB | 300 | ns | |
CB | Capacitive load for each bus line | 400 | pF | ||
t(SP) | Pulse duration of spike suppressed | 0 | 50 | ns | |
I2C Hs MODE TIMING REQUIREMENTS, CB = 400 pF | |||||
f(SCL)(1) | I2C clock frequency | 0 | 1.7 | MHz | |
t(LOW) | SCL clock low period | 320 | ns | ||
t(HIGH) | SCL clock high period | 120 | ns | ||
t(SUSTA) | Repeated start condition setup time | 160 | ns | ||
t(HDSTA) | Hold time after repeated start condition | 160 | ns | ||
t(SUSTO) | Stop condition setup time | 160 | ns | ||
t(SUDAT) | Data setup time | 10 | ns | ||
t(HDDAT) | Data hold time | 0 | 150 | ns | |
tR,SCL | Clock rise time | 20 | 80 | ns | |
tR,SCL1 | Clock rise time after a repeated start condition and after an acknowledge bit | 20 | 160 | ns | |
tF,SCL | Clock fall time | 20 | 80 | ns | |
tR,SDA | Data rise time | 20 | 160 | ns | |
tF,SDA | Data fall time | 20 | 160 | ns | |
CB(2) | Capacitive load for each bus line | 400 | pF | ||
t(SP) | Pulse duration of spike suppressed | 0 | 10 | ns | |
I2C Hs MODE TIMING REQUIREMENTS, CB = 10 pF to 100 pF | |||||
f(SCL) | I2C clock frequency | 0 | 3.4 | MHz | |
t(LOW) | SCL clock low period | 160 | ns | ||
t(HIGH) | SCL clock high period | 60 | ns | ||
t(SUSTA) | Repeated start condition setup time | 160 | ns | ||
t(HDSTA) | Hold time after repeated start condition | 160 | ns | ||
t(SUSTO) | Stop condition setup time | 160 | ns | ||
t(SUDAT) | Data setup time | 10 | ns | ||
t(HDDAT) | Data hold time | 0 | 70 | ns | |
tR,SCL | Clock rise time | 10 | 40 | ns | |
tR,SCL1 | Clock rise time after a repeated start condition and after an acknowledge bit | 10 | 80 | ns | |
tF,SCL | Clock fall time | 10 | 40 | ns | |
tR,SDA | Data rise time | 10 | 80 | ns | |
tF,SDA | Data fall time | 10 | 80 | ns | |
CB(2) | Capacitive load for each bus line | 10 | 100 | pF | |
t(SP) | Pulse duration of spike suppressed | 0 | 10 | ns | |
SPI TIMING REQUIREMENTS | |||||
f(SCLK) | SCLK frequency | 20 | MHz | ||
t(SCLKHIGH) | SCLK high time | 8 | ns | ||
t(SCLKLOW) | SCLK low time | 8 | ns | ||
t(SDISU) | SDI setup time | 5 | ns | ||
t(SDIHD) | SDI hold time | 4 | ns | ||
t(SDODLY)(3) | SDO output delay | 3 | 20 | ns | |
t(CSSU) | CS setup time | 5 | ns | ||
t(CSHD) | CS hold time | 10 | ns | ||
t(CSHIGH) | CS high time | 30 | ns |