Table 7-52 lists the clock net classes for the DDR2 interface. Table 7-53 lists the signal net classes, and associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the termination and routing rules that follow.
|CLOCK NET CLASS||AM335x PIN NAMES|
|CK||DDR_CK and DDR_CKn|
|DQS0||DDR_DQS0 and DDR_DQSn0|
|DQS1||DDR_DQS1 and DDR_DQSn1|