Refer to the PDF data sheet for device specific package drawings
The timing parameter values specified in this data manual do not include delays by board routings. As a good board design practice, such delays must always be taken into account. Timing values may be adjusted by increasing or decreasing such delays. TI recommends using the available I/O buffer information specification (IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers may be used to compensate any timing differences.
For the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the mDDR(LPDDR), DDR2, DDR3, DDR3L memory interface timings are met.