Figure 6-11 shows the recommended oscillator connections when OSC0 is connected to an LVCMOS square-wave digital clock source. The LVCMOS clock source is connected to the XTALIN terminal. The ground for the LVCMOS clock source and VSS_OSC should be connected directly to the nearest PCB digital ground (VSS). In this mode of operation, the XTALOUT terminal should not be used to source any external components. The PCB design should provide a mechanism to disconnect the XTALOUT terminal from any external components or signal traces that may couple noise into OSC0 via the XTALOUT terminal.
The XTALIN terminal has a 15- to 40-kΩ internal pulldown resistor which is enabled when OSC0 is disabled. This internal resistor prevents the XTALIN terminal from floating to an invalid logic level which may increase leakage current through the oscillator input buffer.
|ƒ(XTALIN)||Frequency, LVCMOS reference clock||19.2, 24, 25, or 26||MHz|
|Frequency, LVCMOS reference clock stability and tolerance(1)||–50||50||ppm|
|tdc(XTALIN)||Duty cycle, LVCMOS reference clock period||45%||55%|
|tjpp(XTALIN)||Jitter peak-to-peak, LVCMOS reference clock period||–1%||1%|
|tR(XTALIN)||Time, LVCMOS reference clock rise||5||ns|
|tF(XTALIN)||Time, LVCMOS reference clock fall||5||ns|