The minimum stackup required for routing the AM335x device is a 4-layer stackup as shown in Table 7-47. Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance signal integrity and electromagnetic interference performance, or to reduce the size of the PCB footprint.
|1||Signal||Top signal routing|
|3||Plane||Split power plane|
|4||Signal||Bottom signal routing|
Complete stackup specifications are provided in Table 7-48.
|1||PCB routing and plane layers||4|
|2||Signal routing layers||2|
|3||Full ground layers under DDR2 routing region||1|
|4||Number of ground plane cuts allowed within DDR2 routing region||0|
|5||Full VDDS_DDR power reference layers under DDR2 routing region||1|
|6||Number of layers between DDR2 routing layer and reference ground plane||0|
|7||PCB routing feature size||4||mils|
|8||PCB trace width, w||4||mils|
|9||PCB BGA escape via pad size(2)||18||20||mils|
|10||PCB BGA escape via hole size(2)||10||mils|
|11||Single-ended impedance, Zo(3)||50||75||Ω|