SPRSP56J January   2021  – June 2026 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagrams
    2. 5.2 Pin Attributes
      1.      11
      2.      12
    3. 5.3 Signal Descriptions
      1.      14
      2. 5.3.1  ADC
        1. 5.3.1.1 MAIN Domain
          1.        17
      3. 5.3.2  CPSW3G
        1. 5.3.2.1 MAIN Domain
          1.        20
          2.        21
          3.        22
      4. 5.3.3  CPTS
        1. 5.3.3.1 MAIN Domain
          1.        25
          2.        26
      5. 5.3.4  DDRSS
        1. 5.3.4.1 MAIN Domain
          1.        29
      6. 5.3.5  ECAP
        1. 5.3.5.1 MAIN Domain
          1.        32
          2.        33
          3.        34
      7. 5.3.6  Emulation and Debug
        1. 5.3.6.1 MAIN Domain
          1.        37
        2. 5.3.6.2 MCU Domain
          1.        39
      8. 5.3.7  EPWM
        1. 5.3.7.1 MAIN Domain
          1.        42
          2.        43
          3.        44
          4.        45
          5.        46
          6.        47
          7.        48
          8.        49
          9.        50
          10.        51
      9. 5.3.8  EQEP
        1. 5.3.8.1 MAIN Domain
          1.        54
          2.        55
          3.        56
      10. 5.3.9  FSI
        1. 5.3.9.1 MAIN Domain
          1.        59
          2.        60
          3.        61
          4.        62
          5.        63
          6.        64
          7.        65
          8.        66
      11. 5.3.10 GPIO
        1. 5.3.10.1 MAIN Domain
          1.        69
          2.        70
        2. 5.3.10.2 MCU Domain
          1.        72
      12. 5.3.11 GPMC
        1. 5.3.11.1 MAIN Domain
          1.        75
      13. 5.3.12 I2C
        1. 5.3.12.1 MAIN Domain
          1.        78
          2.        79
          3.        80
          4.        81
        2. 5.3.12.2 MCU Domain
          1.        83
          2.        84
      14. 5.3.13 MCAN
        1. 5.3.13.1 MAIN Domain
          1.        87
          2.        88
      15. 5.3.14 MCSPI
        1. 5.3.14.1 MAIN Domain
          1.        91
          2.        92
          3.        93
          4.        94
          5.        95
        2. 5.3.14.2 MCU Domain
          1.        97
          2.        98
      16. 5.3.15 MDIO
        1. 5.3.15.1 MAIN Domain
          1.        101
      17. 5.3.16 MMC
        1. 5.3.16.1 MAIN Domain
          1.        104
          2.        105
      18. 5.3.17 OSPI
        1. 5.3.17.1 MAIN Domain
          1.        108
      19. 5.3.18 Power Supply
        1.       110
      20. 5.3.19 PRU_ICSSG
        1. 5.3.19.1 MAIN Domain
          1.        113
          2.        114
      21. 5.3.20 Reserved
        1.       116
      22. 5.3.21 SERDES
        1. 5.3.21.1 MAIN Domain
          1.        119
      23. 5.3.22 System and Miscellaneous
        1. 5.3.22.1 Boot Mode Configuration
          1. 5.3.22.1.1 MAIN Domain
            1.         123
        2. 5.3.22.2 Clock
          1. 5.3.22.2.1 MCU Domain
            1.         126
        3. 5.3.22.3 System
          1. 5.3.22.3.1 MAIN Domain
            1.         129
          2. 5.3.22.3.2 MCU Domain
            1.         131
        4. 5.3.22.4 VMON
          1.        133
      24. 5.3.23 TIMER
        1. 5.3.23.1 MAIN Domain
          1.        136
        2. 5.3.23.2 MCU Domain
          1.        138
      25. 5.3.24 UART
        1. 5.3.24.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 5.3.24.2 MCU Domain
          1.        149
          2.        150
      26. 5.3.25 USB
        1. 5.3.25.1 MAIN Domain
          1.        153
    4. 5.4 Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Operating Performance Points
    6. 6.6  Power Consumption Summary
    7. 6.7  Electrical Characteristics
      1. 6.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 6.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 6.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 6.7.4  eMMCPHY Electrical Characteristics
      5. 6.7.5  SDIO Electrical Characteristics
      6. 6.7.6  LVCMOS Electrical Characteristics
      7. 6.7.7  ADC12B Electrical Characteristics
      8. 6.7.8  USB2PHY Electrical Characteristics
      9. 6.7.9  SerDes PHY Electrical Characteristics
      10. 6.7.10 DDR Electrical Characteristics
    8. 6.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.8.2 Hardware Requirements
      3. 6.8.3 Programming Sequence
      4. 6.8.4 Impact to Your Hardware Warranty
    9. 6.9  Thermal Resistance Characteristics
      1. 6.9.1 Thermal Resistance Characteristics
    10. 6.10 Temperature Sensor Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Requirements
        1. 6.11.2.1 Power Supply Slew Rate Requirement
        2. 6.11.2.2 Power Supply Sequencing
          1. 6.11.2.2.1 Power-Up Sequencing
          2. 6.11.2.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 Reset Timing
        2. 6.11.3.2 Safety Signal Timing
        3. 6.11.3.3 Clock Timing
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 6.11.4.1.1.1 Load Capacitance
            2. 6.11.4.1.1.2 Shunt Capacitance
          2. 6.11.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 6.11.4.2 Output Clocks
        3. 6.11.4.3 PLLs
        4. 6.11.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 6.11.5 Peripherals
        1. 6.11.5.1  CPSW3G
          1. 6.11.5.1.1 CPSW3G MDIO Timing
          2. 6.11.5.1.2 CPSW3G RMII Timing
          3. 6.11.5.1.3 CPSW3G RGMII Timing
          4. 6.11.5.1.4 CPSW3G IOSETs
        2. 6.11.5.2  DDRSS
        3. 6.11.5.3  ECAP
        4. 6.11.5.4  EPWM
        5. 6.11.5.5  EQEP
        6. 6.11.5.6  FSI
        7. 6.11.5.7  GPIO
        8. 6.11.5.8  GPMC
          1. 6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 6.11.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 6.11.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 6.11.5.8.4 GPMC0 IOSETs
        9. 6.11.5.9  I2C
        10. 6.11.5.10 MCAN
        11. 6.11.5.11 MCSPI
          1. 6.11.5.11.1 MCSPI — Controller Mode
          2. 6.11.5.11.2 MCSPI — Peripheral Mode
        12. 6.11.5.12 MMCSD
          1. 6.11.5.12.1 MMC0 - eMMC Interface
            1. 6.11.5.12.1.1 Legacy SDR Mode
            2. 6.11.5.12.1.2 High Speed SDR Mode
            3. 6.11.5.12.1.3 High Speed DDR Mode
            4. 6.11.5.12.1.4 HS200 Mode
          2. 6.11.5.12.2 MMC1 - SD/SDIO Interface
            1. 6.11.5.12.2.1 Default Speed Mode
            2. 6.11.5.12.2.2 High Speed Mode
            3. 6.11.5.12.2.3 UHS–I SDR12 Mode
            4. 6.11.5.12.2.4 UHS–I SDR25 Mode
            5. 6.11.5.12.2.5 UHS–I SDR50 Mode
            6. 6.11.5.12.2.6 UHS–I DDR50 Mode
            7. 6.11.5.12.2.7 UHS–I SDR104 Mode
        13. 6.11.5.13 CPTS
        14. 6.11.5.14 OSPI
          1. 6.11.5.14.1 OSPI0 PHY Mode
            1. 6.11.5.14.1.1 OSPI0 With PHY Data Training
            2. 6.11.5.14.1.2 OSPI0 Without Data Training
              1. 6.11.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 6.11.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 6.11.5.14.2 OSPI0 Tap Mode
            1. 6.11.5.14.2.1 OSPI0 Tap SDR Timing
            2. 6.11.5.14.2.2 OSPI0 Tap DDR Timing
        15. 6.11.5.15 PCIe
        16. 6.11.5.16 PRU_ICSSG
          1. 6.11.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 6.11.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 6.11.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 6.11.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 6.11.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 6.11.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 6.11.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 6.11.5.16.2.1 PRU_ICSSG PWM Timing
          3. 6.11.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.16.3.1 PRU_ICSSG IEP Timing
          4. 6.11.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.16.4.1 PRU_ICSSG UART Timing
          5. 6.11.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 6.11.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 6.11.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 6.11.5.16.6.2 PRU_ICSSG MII Timing
            3. 6.11.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 6.11.5.17 Timers
        18. 6.11.5.18 UART
        19. 6.11.5.19 USB
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 Trace
        2. 6.11.6.2 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-A53 Subsystem
      2. 7.2.2 Arm Cortex-R5F Subsystem (R5FSS)
      3. 7.2.3 Arm Cortex-M4F (M4FSS)
    3. 7.3 Accelerators and Coprocessors
      1. 7.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 7.4 Other Subsystems
      1. 7.4.1 PDMA Controller
      2. 7.4.2 Peripherals
        1. 7.4.2.1  ADC
        2. 7.4.2.2  DCC
        3. 7.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 7.4.2.4  ECAP
        5. 7.4.2.5  EPWM
        6. 7.4.2.6  ELM
        7. 7.4.2.7  ESM
        8. 7.4.2.8  GPIO
        9. 7.4.2.9  EQEP
        10. 7.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 7.4.2.11 I2C
        12. 7.4.2.12 MCAN
        13. 7.4.2.13 MCRC Controller
        14. 7.4.2.14 MCSPI
        15. 7.4.2.15 MMCSD
        16. 7.4.2.16 OSPI
        17. 7.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 7.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 7.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 7.4.2.20 Dual Mode Timer (DMTIMER)
        21. 7.4.2.21 UART
        22. 7.4.2.22 Universal Serial Bus Subsystem (USBSS)
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 Power Supply
        1. 8.1.1.1 Power Supply Designs
        2. 8.1.1.2 Power Distribution Network Implementation Guidance
      2. 8.1.2 External Oscillator
      3. 8.1.3 JTAG, EMU, and TRACE
      4. 8.1.4 Unused Pins
    2. 8.2 Peripheral- and Interface-Specific Design Information
      1. 8.2.1 DDR Board Design and Layout Guidelines
      2. 8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 8.2.2.2 External Board Loopback
        3. 8.2.2.3 DQS (only available in Octal SPI devices)
      3. 8.2.3 USB VBUS Design Guidelines
      4. 8.2.4 System Power Supply Monitor Design Guidelines
      5. 8.2.5 High Speed Differential Signal Routing Guidance
      6. 8.2.6 Thermal Solution Guidance
    3. 8.3 Clock Routing Guidelines
      1. 8.3.1 Oscillator Routing
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.11.5.8.1 GPMC and NOR Flash — Synchronous Mode

Table 6-58 and Table 6-59 present timing requirements and switching characteristics for GPMC and NOR Flash - Synchronous Mode.

Table 6-58 GPMC and NOR Flash Timing Requirements — Synchronous Mode see Figure 6-39, Figure 6-40, and Figure 6-43
NO. PARAMETER DESCRIPTION MODE(4) MIN MAX MIN MAX UNIT
32-bit data bus (up to 100MHz)(1) 16-bit data bus (up to 133MHz)(1)
F12 tsu(dV-clkH) Setup time, GPMC0_AD[n:0](1) valid before GPMC0_CLK high div_by_1_mode 1.81 1.12 ns
not_div_by_1_mode 1.06 3.5 ns
F13 th(clkH-dV) Hold time, GPMC0_AD[n:0](1) valid after GPMC0_CLK high div_by_1_mode 2.29 2.29 ns
not_div_by_1_mode 2.29 2.29 ns
F21 tsu(waitV-clkH) Setup time, GPMC0_WAIT[j](2)(3) valid before GPMC0_CLK high div_by_1_mode 1.81 1.12 ns
not_div_by_1_mode 1.06 3.5 ns
F22 th(clkH-waitV) Hold time, GPMC0_WAIT[j](2)(3) valid after GPMC0_CLK high div_by_1_mode 2.29 2.29 ns
not_div_by_1_mode 2.29 2.29 ns
(1) Synchronous Mode supports a 32-bit data bus (GPMC0_AD[31:0]) with GPMC0_CLK up to 100MHz and a 16-bit data bus (GPMC0_AD[15:0]) with GPMC0_CLK up to 133MHz. Select the clock source of GPMC0_FCLK which feeds GPMC0_CLK by writing to the CTRLMMR_GPMC0_CLKSEL register:
  • 133MHz: CLK_SEL = 0h - MAIN_PLL0_HSDIV3_CLKOUT (default)
  • 100MHz: CLK_SEL = 1h - MAIN_PLL2_HSDIV3_CLKOUT
(2) In GPMC_WAIT[j], j is equal to 0 or 1.
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-Purpose Memory Controller (GPMC) section in the device TRM.
(4) For div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
    • GPMC0_CLK frequency = GPMC0_FCLK frequency

For not_div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
    • GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4)
Table 6-59 GPMC and NOR Flash Switching Characteristics – Synchronous Mode see Figure 6-39, Figure 6-40, Figure 6-41, Figure 6-42, and Figure 6-43
NO. PARAMETER DESCRIPTION MIN MAX UNIT
F0 tc(clk) Cycle time, GPMC0_CLK(16) 7.52(1) ns
F1 tw(clkH) Typical pulse duration, GPMC0_CLK high 0.475P(14) - 0.3 ns
F1 tw(clkL) Typical pulse duration, GPMC0_CLK low 0.475P(14) - 0.3 ns
F2 td(clkH-csn[i]V) Delay time, GPMC0_CLK rising edge to GPMC0_CSn[i](13) transition F(6) - 2.2 F(6) + 1.31 ns
F3 td(clkH-csn[i]IV) Delay time, GPMC0_CLK rising edge to GPMC0_CSn[i](13) invalid D(5) - 2.2 D(5) + 1.31 ns
F4 td(aV-clk) Delay time, GPMC0_A[27:1] valid to GPMC0_CLK first edge B(3) - 2.3 B(3) + 4.5 ns
F5 td(clkH-aIV) Delay time, GPMC0_CLK rising edge to GPMC0_A[27:1] invalid -2.3 4.5 ns
F6 td(be[x]nV-clk) Delay time, GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n valid to GPMC0_CLK first edge B(3) - 2.3 B(3) + 1.9 ns
F7 td(clkH-be[x]nIV) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n invalid D(5) - 2.3 D(5) + 1.9 ns
F8 td(clkH-advn) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE transition G(7) - 2.3 G(7) + 4.5 ns
F9 td(clkH-advnIV) Delay time, GPMC0_CLK rising edge to GPMC0_ADVn_ALE invalid D(5) - 2.3 D(5) + 4.5 ns
F10 td(clkH-oen) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn transition H(8) - 2.3 H(8) + 3.5 ns
F11 td(clkH-oenIV) Delay time, GPMC0_CLK rising edge to GPMC0_OEn_REn invalid D(5) - 2.3 D(5) + 3.5 ns
F14 td(clkH-wen) Delay time, GPMC0_CLK rising edge to GPMC0_WEn transition I(9) - 2.3 I(9) + 4.5 ns
F15 td(clkH-do) Delay time, GPMC0_CLK rising edge to GPMC0_AD[n:0](1) transition(10) -2.3 2.7 ns
F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_AD[n:0](1) transition(11) -2.3 2.7 ns
F15 td(clkL-do) Delay time, GPMC0_CLK falling edge to GPMC0_AD[n:0](1) transition(12) -2.3 2.7 ns
F17 td(clkH-be[x]n) Delay time, GPMC0_CLK rising edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(10) -2.3 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(11) -2.3 1.9 ns
F17 td(clkL-be[x]n) Delay time, GPMC0_CLK falling edge to GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n transition(12) -2.3 1.9 ns
F18 tw(csnV) Pulse duration, GPMC0_CSn[i](13) low A(2) ns
F19 tw(be[x]nV) Pulse duration, GPMC0_BE0n_CLE, GPMC0_BE1n, GPMC0_BE2n, GPMC0_BE3n low C(4) ns
F20 tw(advnV) Pulse duration, GPMC0_ADVn_ALE low K(15) ns
(1) Synchronous Mode supports a 32-bit data bus (GPMC0_AD[31:0]) with GPMC0_CLK up to 100MHz and a 16-bit data bus (GPMC0_AD[15:0]) with GPMC0_CLK up to 133MHz. Select the clock source of GPMC0_FCLK which feeds GPMC0_CLK by writing to the CTRLMMR_GPMC0_CLKSEL register:
  • 133MHz: CLK_SEL = 0h - MAIN_PLL0_HSDIV3_CLKOUT (default)
  • 100MHz: CLK_SEL = 1h - MAIN_PLL2_HSDIV3_CLKOUT
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
With n being the page burst access number.
(3) Address bus / Byte Enables become valid at start of cycle, GPMC0_CLK activation time may be delayed after start of cycle B = ClkActivationTime × GPMC0_FCLK(14)
(4) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
With n being the page burst access number.
(5) For single read: D = (RdCycleTime - RdAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For single write: D = (WrCycleTime - WrAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst read: D = (RdCycleTime - RdAccessTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For burst write: D = (WrCycleTime - WrAccessTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
With n being the page burst access number.
(6) For CSn falling edge (CS activated):
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

For CSn rising edge (CS deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSRdOffTime are odd) or (ClkActivationTime and CSRdOffTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For CSn rising edge (CS deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and CSWrOffTime are odd) or (ClkActivationTime and CSWrOffTime are even)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • F = 0.5 × CSExtraDelay × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime) is a multiple of 3)
    • F = (1 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • F = (2 + 0.5 × CSExtraDelay) × GPMC0_FCLK(14) if ((CSWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:
  • Case GPMCFCLKDIVIDER = 0:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • G = 0.5 × ADVExtraDelay × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
    • G = (1 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
    • G = (2 + 0.5 × ADVExtraDelay) × GPMC0_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • H = 0.5 × OEExtraDelay × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
    • H = (1 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • H = (2 + 0.5 × OEExtraDelay) × GPMC0_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK(14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):
  • Case GPMCFCLKDIVIDER = 0:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK (14)
  • Case GPMCFCLKDIVIDER = 1:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) otherwise
  • Case GPMCFCLKDIVIDER = 2:
    • I = 0.5 × WEExtraDelay × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
    • I = (1 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
    • I = (2 + 0.5 × WEExtraDelay) × GPMC0_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(10) Case GPMC0_CLK in div_by_1_mode(17), first transfer only: Data and byte enables transition on rise edge of GPMC0_CLK
  • Non-multiplexed mode: data transition at start of cycle
  • Multiplexed mode: data transition at WRDATAONADMUXBUS × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
(11) Case GPMC0_CLK in div_by_1_mode(17), all data and byte enables after initial transfer: Data and byte enables transition on fall edge of GPMC0_CLK (Half cycle of GPMC0_CLK)
(12) Case GPMC0_CLK in not_div_by_1_mode(17) (GPMC0_CLK divided down from GPMC0_FCLK): All data and byte enables transition on fall edge of GPMC0_CLK (Half cycle of GPMC0_CLK). ClkActivationTime, GPMCFCLKDIVIDER, RDACCESSTIME/WRACCESSTIME, and PAGEBURSTACCESSTIME configuration must be configured to enforce data and byte enables transition on falling edge of GPMC0_CLK (to be latched on rise edge of GPMC0_CLK)
(13) In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
(14) P = GPMC0_CLK period in ns
(15) For read: K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC0_FCLK(14)
(16) Related to the GPMC0_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the GPMC0_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(17) For div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
    • GPMC0_CLK frequency = GPMC0_FCLK frequency

For not_div_by_1_mode:
  • GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
    • GPMC0_CLK frequency = GPMC0_FCLK frequency / (2 to 4)
AM6442 AM6441 AM6422 AM6421 AM6412 AM6411 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC0_WAIT[j], j is equal to 0 or 1.
Figure 6-39 GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)
AM6442 AM6441 AM6422 AM6421 AM6412 AM6411 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC0_WAIT[j], j is equal to 0 or 1.
Figure 6-40 GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)
AM6442 AM6441 AM6422 AM6421 AM6412 AM6411 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC0_WAIT[j], j is equal to 0 or 1.
Figure 6-41 GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)
AM6442 AM6441 AM6422 AM6421 AM6412 AM6411 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC0_WAIT[j], j is equal to 0 or 1.
Figure 6-42 GPMC and Multiplexed NOR Flash — Synchronous Burst Read
AM6442 AM6441 AM6422 AM6421 AM6412 AM6411 GPMC and Multiplexed NOR Flash — Synchronous Burst Write
A. In GPMC0_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC0_WAIT[j], j is equal to 0 or 1.
Figure 6-43 GPMC and Multiplexed NOR Flash — Synchronous Burst Write