SLUSDL9A June 2019 – January 2021 BQ25125
The device uses an I2C compatible interface to program and read many parameters. I2C is a 2-wire serial interface developed by NXP. The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O terminals, SDA and SCL. A master device, usually a microcontroller or digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.
The device works as a slave and supports the following data transfer modes, as defined in the I2C BUS Specification: standard mode (100 kbps) and fast mode (400kbps). The interface adds flexibility to the battery management solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. The I2C circuitry is powered from the battery in active battery mode. The battery voltage must stay above V(BATUVLO) when no VIN is present to maintain proper operation. The host must also wait for SYS to come up before starting communication with the part.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The device only supports 7-bit addressing. The device 7-bit address is 6A (8-bit shifted address is D4).
To avoid I2C hang-ups, a timer (tI2CRESET) runs during I2C transactions. If the SDA line is held low longer than tI2CRESET, any additional commands are ignored and the I2C engine is reset. The timeout is reset with START and repeated START conditions and stops when a valid STOP condition is sent.