SLUSDL9A June 2019 – January 2021 BQ25125
The device contains two open-drain outputs that signal its status and are valid only after the device has completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent. The PG output signals when a valid input source is connected. PG pulls to GND when VIN > VUVLO, VIN> VBAT+VSLP and VIN < VOVP. PG is high-impedance when the input power is not within specified limits. Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor, or use with an LED for visual indication.
The PG pin can be configured as a MR shifted (MRS) output when the PGB_MRS bit is set to 1. PG is high-impedance when the MR input is not low, and PG pulls to GND when the MR input is below VOL(TH_MRS). Connect PG to the desired logic voltage rail using a 1-kΩ to 100-kΩ resistor.
The INT pin is pulled low during charging when the EN_INT bit is set to 1 and interrupts are pulled high. When EN_INT is set to 0, charging status is not indicated on the INT pin. When charge is complete or disabled, INT is high impedance. The charge status is valid whether it is the first charge or recharge. When a fault occurs, a 128 µs pulse (interrupt) is sent on INT to notify the host.