SLUSDL9A June 2019 – January 2021 BQ25125
When a valid input source is connected (VIN > VUVLO and V(BAT) + VSLP < VIN < VOVP and VIN > VIN(DPM)), the CE bit in the control register determines whether a charge cycle is initiated. When the CE bit is 1 and a valid input source is connected, the battery discharge FET is turned off, and the output at SYS is regulated depending on the output configuration. A charge cycle is initiated when the CE bit is written to a 0. Alternatively, the CD input can be used to enable and disable charge.
The device supports multiple battery chemistries for single-cell applications. Charging is done through the internal battery MOSFET. There are several loops that influence the charge current: constant current loop (CC), constant voltage loop (CV), input current limit, and VIN(DPM). Note that VDPPM loop feature found on similar chargers is disabled by default. During the charging process, all loops are enabled and the one that is dominant takes control.
The charge current is regulated to ICHARGE until the voltage between BAT and GND reaches the regulation voltage. The voltage between BAT and GND is regulated to VBATREG (CV Mode) while the charge current naturally tapers down. When termination is enabled, the device monitors the charging current during the CV mode, and once the charge current tapers down to the termination threshold, ITERM, and the battery voltage is above the recharge threshold, the device terminates charge, and turns off the battery charging FET. Termination is disabled when any loop is active other than CV.