SLUSBH2G March   2013  – March 2019


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Schematic
      2.      Charger Efficiency vs Input Voltage
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Power Point Tracking
      2. 7.3.2 Battery Undervoltage Protection
      3. 7.3.3 Battery Overvoltage Protection
      4. 7.3.4 Battery Voltage within Operating Range (VBAT_OK Output)
      5. 7.3.5 Storage Element / Battery Management
      6. 7.3.6 Programming OUT Regulation Voltage
      7. 7.3.7 Step Down (Buck) Converter
      8. 7.3.8 Nano-Power Management and Efficiency
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Boost Charger Disabled (Ship Mode) - (VSTOR > VSTOR_CHGEN and EN = HIGH)
      2. 7.4.2 Cold-Start Operation (VSTOR < VSTOR_CHGEN, VIN_DC > VIN(CS) and PIN > PIN(CS), EN = don't care)
      3. 7.4.3 Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN and EN = LOW )
        1. Buck Converter Enabled (VSTOR > VBAT_UV, EN = LOW and VOUT_EN = HIGH )
      4. 7.4.4 Thermal Shutdown
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Energy Harvester Selection
      2. 8.1.2 Storage Element Selection
      3. 8.1.3 Inductor Selection
        1. Boost Charger Inductor Selection
        2. Buck Converter Inductor Selection
      4. 8.1.4 Capacitor Selection
        1. VREF_SAMP Capacitance
        2. VIN_DC Capacitance
        3. VSTOR Capacitance
        4. VOUT Capacitance
        5. Additional Capacitance on VSTOR or VBAT
    2. 8.2 Typical Applications
      1. 8.2.1 Solar Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 TEG Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 8.2.3 Piezoelectric Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Main Boost Charger Enabled (VSTOR > VSTOR_CHGEN and EN = LOW )

One way to avoid cold start is to attach a partially charged storage element as shown in Figure 23.

bq25570 batteryattach_startup_505_slusbj3.pngFigure 23. Charger Operation after a Partially Charged Storage Element is Attached and Harvester Power is Available

When no input source is attached, the VSTOR node should be discharged to ground before attaching a storage element. Hot-plugging a storage element that is charged (for example, the battery protector PFET is closed) and with the VSTOR node more than 100 mV above ground results in the PFET between VSTOR and VBAT remaining off until an input source is attached.

Assuming the voltages on VSTOR and VBAT are both below 100 mV, when a charged storage element is attached (that is, hot-plugged) to VBAT, the IC

  1. first turns on the internal PFET between the VSTOR and VBAT pins for tBAT_HOT_PLUG (45 ms) in order to charge VSTOR to VSTOR_CHGEN then turns off the PFET to prevent the battery from overdischarge,
  2. then performs an initialization pulse on VRDIV to reset the feedback voltages,
  3. then disables the charger for 32 ms (typical) to allow the VIN_DC voltage to rise to the harvester's open-circuit voltage which will be used as the input voltage regulation reference voltage until the next MPPT sampling cycle and
  4. lastly performs its first feedback sampling using VRDIV, approximately 64 ms after the initialization pulse.

If the VSTOR pin voltage remains above the internal under voltage threshold (VBAT_UV) for the additional 64 ms after the VRDIV initialization pulse (following the 45-ms PFET on time), the internal PFET turns back on and the main boost charger begins to charge the storage element assuming there is sufficient power available from the harvester at the VIN_DC pin. If VSTOR does not reach the VBAT_UV threshold, then the PFET remains off until the main boost charger can raise the VSTOR voltage to VBAT_UV. If a system load tied to VSTOR discharges VSTOR below VSTOR_GEN or below VBAT_UV during the 32 ms initial MPPT reference voltage measurement or within 110 ms after hot plug, it is recommended to add an external PFET between the system load and VSTOR. An inverted VBAT_OK signal provided by VB_SEC_ONcan be used to drive the gate of this system-isolating, external PFET. Otherwise, the VSTOR voltage waveform will have incremental pulses as the IC turns on and off the internal PFET controlled by VBAT_UV or cycles between cold-start and main boost charger operation.

Once VSTOR is above VSTOR_CHGEN but less than VBAT_V and VIN_DC > VIN(DC)-MIN = 100 mV, the main boost charger extracts power from its source by employing pulse frequency modulation (PFM) mode of control to regulate the voltage at VIN_DC close to the desired reference voltage. The reference voltage is set by the MPPT circuitry as described in the features section. Input voltage regulation is obtained by transferring charge from the input to VSTOR only when the input voltage is higher than the voltage on pin VREF_SAMP. The current through the inductor is controlled through internal current sense circuitry. The peak current in the inductor is incremented internally in three pre-determined levels (~50 mA, ~100 mA and finally I-CHG(CBC_LIM)) in order to maintain high efficiency of the charger across a wide input current range. When in discontinous mode, the boost charger can transfer up to a maximum of 100 mA average input current with I-CHG(CBC_LIM) = 230mA typical peak inductor current. The boost charger is disabled when the voltage on VSTOR reaches the user set VBAT_OV threshold to protect the battery connected at VBAT from overcharging. In order for the battery to charge to VBAT_OV, the input power must exceed the power needed for the load on VSTOR. See the Energy Harvester Selection applications section for guidance on minimum input power requirements.

Steady state operation for the boost charger is shown in Figure 23. These plots highlight the inductor current, the VSTOR voltage ripple, input voltage regulation and the LBOOST switching node. The cycle-by-cycle minor switching frequency is a function of each the converter's inductor value, peak current limit and voltage levels on each side of each inductor. Once the VSTOR capacitor, CSTOR, droops below a minimum value, the hysteretic switching repeats.