SLUSE97 November   2023 BQ76905

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  REGOUT LDO
    8. 6.8  Voltage References
    9. 6.9  Coulomb Counter
    10. 6.10 Coulomb Counter Digital Filter
    11. 6.11 Current Wake Detector
    12. 6.12 Analog-to-Digital Converter
    13. 6.13 Cell Balancing
    14. 6.14 Internal Temperature Sensor
    15. 6.15 Thermistor Measurement
    16. 6.16 Hardware Overtemperature Detector
    17. 6.17 Internal Oscillator
    18. 6.18 Charge and Discharge FET Drivers
    19. 6.19 Comparator-Based Protection Subsystem
    20. 6.20 Timing Requirements—I2C Interface, 100-kHz Mode
    21. 6.21 Timing Requirements—I2C Interface, 400-kHz Mode
    22. 6.22 Timing Diagram
    23. 6.23 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Configuration
      1. 7.3.1 Commands and Subcommands
      2. 7.3.2 Configuration Using OTP or Registers
      3. 7.3.3 Device Security
    4. 7.4 Device Hardware Features
      1. 7.4.1  Voltage ADC
      2. 7.4.2  Coulomb Counter and Digital Filters
      3. 7.4.3  Protection FET Drivers
      4. 7.4.4  Voltage References
      5. 7.4.5  Multiplexer
      6. 7.4.6  LDOs
      7. 7.4.7  Standalone Versus Host Interface
      8. 7.4.8  ALERT Pin Operation
      9. 7.4.9  Low Frequency Oscillator
      10. 7.4.10 I2C Serial Communications Interface
    5. 7.5 Measurement Subsystem
      1. 7.5.1 Voltage Measurement
        1. 7.5.1.1 Voltage ADC Scheduling
        2. 7.5.1.2 Unused VC Pins
        3. 7.5.1.3 General Purpose ADCIN Functionality
      2. 7.5.2 Current Measurement and Charge Integration
      3. 7.5.3 Internal Temperature Measurement
      4. 7.5.4 Thermistor Temperature Measurement
      5. 7.5.5 Factory Trim and Calibration
    6. 7.6 Protection Subsystem
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 CHG Detector
      4. 7.6.4 Cell Open-Wire Protection
      5. 7.6.5 Diagnostic Checks
    7. 7.7 Cell Balancing
    8. 7.8 Device Operational Modes
      1. 7.8.1 Overview of Operational Modes
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Random Cell Connection Support
      5. 8.2.5 Startup Timing
      6. 8.2.6 FET Driver Turn-Off
      7. 8.2.7 Usage of Unused Pins
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.6 FET Driver Turn-Off

The low-side CHG and DSG FET drivers operate differently when they are triggered to turn off their respective FET. The DSG driver includes an internal switch that drives the DSG pin toward the VSS pin level when the driver is disabled. The driver is specified with a maximum fall time into a 20-nF capacitive load, with 100-Ω series resistance between the DSG pin and the DSG gate. If the driver is used with a larger capacitive load, the fall time generally increases. The system designer can optimize the series resistance value based on the board components and DSG FET(s) used.

The external series gate resistor between the DSG pin and the DSG FET gate is used to adjust the speed of the turn-off transient. A low resistance (such as 100 Ω) provides a fast turn-off during a short circuit event, but this can result in an overly large inductive spike at the top of stack when the FET is disabled. A larger resistor value (such as 1 kΩ or 4.7 kΩ) reduces this speed and the corresponding inductive spike level.

The CHG FET driver discharges the CHG pin toward the VSS pin level, but it includes an additional series PFET in order to support voltages below VSS. This is generally needed when a pack is heavily discharged, for example, if cells in a 5S pack are at 2.5 V per cell, then PACK+ = 12.5 V relative to device VSS. Then if a charger is attached while the CHG FET is disabled and applies a full charge voltage across PACK+ relative to PACK-, such as 4.3 V per cell, or 21.5 V for the 5S pack, this results in PACK– dropping to approximately –9 V relative to VSS. In order to keep the CHG FET disabled, its gate voltage must drop to near this –9 V level.

To support this type of case, the CHG FET driver in BQ76905 is designed to withstand voltages as low as –25 V (recommended) relative to the VSS pin voltage by including a series PFET at the pin, with its gate connected to VSS. When the CHG driver is disabled, the driver pulls the pin voltage downward. As the pin voltage nears VSS, the PFET is disabled, so the pin becomes high impedance. At this point, the external gate-source resistor on the CHG FET pulls the pin voltage lower to the PACK– level, keeping the CHG FET disabled.

Oscilloscope captures of CHG and DSG driver turn-off are shown below, with the pins driving the gates of CSD18532Q5B NFETs, which have a typical Ciss of 3900 pF. Figure 8-12 shows the signals when using a 1.35-kΩ series gate resistor between the DSG pin and the FET gate, and a 2A load connected between PACK+ and PACK–.

GUID-5855723E-315B-40B1-A40D-EB8EEBE05AB4-low.png Figure 8-6 Moderate Speed DSG FET Turn-Off, Using a 1.35-kΩ Series Gate Resistor, and a 2A Load between PACK+ and PACK–.

A slower turn-off case is shown in Figure 8-7, using a 4.5-kΩ series gate resistor, and a 2A load between PACK+ and PACK–.

GUID-7421B99E-CC5F-43A7-879A-CF0F425A6146-low.png Figure 8-7 A Slower Turn-Off Case Using a 4.5-kΩ Series Gate Resistor

A fast turn-off case is shown in Figure 8-8, in which a 100-Ω series gate resistor is used between the DSG pin and the FET gate.

GUID-D36B3132-08E0-4B83-B9D2-68A8C7824945-low.png Figure 8-8 A Fast Turn-Off Case with a 100-Ω Series Gate Resistor