SBOS948F February   2019  – May 2021 BUF634A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Wide-Bandwidth Mode
    6. 7.6 Electrical Characteristics: Low-Quiescent Current Mode
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Current
      2. 8.3.2 Thermal Shutdown
      3. 8.3.3 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Adjustable Bandwidth
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 High-Frequency Applications
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Dissipation and Thermal Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 SOIC Layout Guidelines (D Package Without a Thermal Pad)
      2. 11.1.2 HSOIC Layout Guidelines (DDA Package With a Thermal Pad)
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 TINA-TI (Free Software Download)
        2. 12.1.2.2 TI Precision Designs
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDA|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-DFCFA262-DE9E-4AEB-957F-0FCF756C8D85-low.gifFigure 6-1 D and DDA Packages8-Pin SOIC, 8-Pin HSOIC with Thermal PadTop View
GUID-55F17D1D-8AB3-48C3-AF59-9F0B12E7FD03-low.gifFigure 6-2 DRB Package8-Pin VSON with Thermal PadTop View
Table 6-1 Pin Functions
PIN I/O(2) DESCRIPTION
NAME DDA(1) DRB(1) D
BW 1 1 1 I Bandwidth adjust pin. Connect the BW pin to the V– pin for wide-BW mode and leave the BW pin floating for low-IQ mode. See the Adjustable Bandwidth section.
NC 2, 5, 8 2, 5, 8 2, 5, 8 — No internal connection
V– 4 4 4 P Negative power supply
V+ 7 7 7 P Positive power supply
VIN 3 3 3 I Input
VO 6 6 6 O Output
Thermal Pad — — Thermal pad. Must be electrically shorted to V–.
(1) The DRB and DDA packages include a thermal pad on the backside of the device. The thermal pad must be connected to the same potential as V–. Connect the thermal pad and V– to a heat-spreading plane to achieve low thermal impedance. The thermal pad can also be unused (not connected to any heat-spreading plane or voltage), thus giving an overall higher thermal impedance.
(2) I = input, O = output, P = power.