SWRS284C April   2024  â€“ October 2025 CC3350 , CC3351

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 System Diagram
  6. 5 Pin Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Electrical Characteristics
    5. 6.5  Thermal Resistance Characteristics
    6. 6.6  WLAN Performance: 2.4GHz Receiver Characteristics
    7. 6.7  WLAN Performance: 2.4GHz Transmitter Power
    8. 6.8  WLAN Performance: 5GHz Receiver Characteristics
    9. 6.9  WLAN Performance: 5GHz Transmitter Power
    10. 6.10 BLE Performance: Receiver Characteristics
    11. 6.11 BLE Performance: Transmitter Characteristics
    12. 6.12 Current Consumption: 2.4GHz WLAN Static Modes
    13. 6.13 Current Consumption: 5GHz WLAN Static Modes
    14. 6.14 Current Consumption: 2.4GHz WLAN Use Cases
    15. 6.15 Current Consumption: 5GHz WLAN Use Cases
    16. 6.16 Current Consumption: BLE Static Modes
    17. 6.17 Current Consumption: BLE Use Cases
    18. 6.18 Current Consumption: Device Modes
    19. 6.19 Timing and Switching Characteristics
      1. 6.19.1 Power Supply Sequencing
      2. 6.19.2 Clocking Specifications
        1. 6.19.2.1 Slow Clock Generated Internally
        2. 6.19.2.2 Slow Clock Using an External Oscillator
          1. 6.19.2.2.1 External Slow Clock Requirements
        3. 6.19.2.3 Fast Clock Using an External Crystal (XTAL)
          1. 6.19.2.3.1 External Fast Clock XTAL Specifications
    20. 6.20 Interface Timing Characteristics
      1. 6.20.1 SDIO Timing Specifications
        1. 6.20.1.1 SDIO Timing Diagram—Default Speed
        2. 6.20.1.2 SDIO Timing Parameters: Default Speed
        3. 6.20.1.3 SDIO Timing Diagram—High Speed
        4. 6.20.1.4 SDIO Timing Parameters: High Speed
      2. 6.20.2 SPI Timing Specifications
        1. 6.20.2.1 SPI Timing Diagram
        2. 6.20.2.2 SPI Timing Parameters
      3. 6.20.3 UART 4-Wire Interface
        1. 6.20.3.1 UART Timing Diagram
        2. 6.20.3.2 UART Timing Parameters
  8. 7 Detailed Description
    1. 7.1 WLAN Features
    2. 7.2 Bluetooth Low Energy Features
  9. 8 Applications, Implementation, and Layout
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Nomenclature Boilerplate
    3. 9.3 Tools and Software
    4. 9.4 Documentation Support
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.2 Pin Attributes

Table 5-1 Pin Attributes
PINSIGNAL NAMETYPEDIR (I/O)VOLTAGE LEVELSHUTDOWN STATE(1)STATE AFTER POWER-UPDESCRIPTION
1PA_LDO_OUTAnalogRF power amplifier LDO output
2RF_BGRFI/OBluetooth Low Energy and WLAN 2.4GHz RF port
3GNDGNDGND
4VDDA_IN1POW1.8V supply for analog domain
5VDDA_IN2POW1.8V supply for analog domain
6HFXT_PAnalogSineXTAL_P
7HFXT_MAnalogXTAL_N
8COEX_GRANT(2)DigitalOVIOPDPDExternal coexistence interface - grant
9COEX_PRIORITY(2)DigitalIVIOPUPUExternal coexistence interface - priority
10COEX_REQ(2)DigitalIVIOPUPUExternal coexistence interface - request
11UART RTSDigitalOVIOPUPUDevice RTS signal - flow control for BLE HCI
12UART CTSDigitalIVIOPUPUDevice CTS signal - flow control for BLE HCI
13UART RXDigitalIVIOPUPUUART RX for BLE HCI
14UART TXDigitalOVIOPUPUUART TX for BLE HCI
15ANT_SEL(2)DigitalOVIOPDPDAntenna select control line
16GNDGNDGND
17VIOPOW1.8V IO supply
18SDIO CMDDigitalI/OVIOHiZHiZSDIO command or SPI PICO
19SDIO CLKDigitalIVIOHiZHiZSDIO clock or SPI clock
20GNDGNDGND
21SDIO D3DigitalI/OVIOHiZPUSDIO data D3 or SPI CS
22SDIO D2DigitalI/OVIOHiZHiZSDIO data D2
23SDIO D1DigitalI/OVIOHiZHiZSDIO data D1
24SDIO D0DigitalI/OVIOHiZHiZSDIO data D0 or SPI POCI
25GNDGNDGND
26SWCLKDigitalIVIOPDPDSerial wire debug clock
27SWDIODigitalI/OVIOPUPUSerial wire debug I/O
28LOGGER(3)DigitalOVIOPUPUTracer (UART TX debug logger)
29HOST_IRQ_WL(3)DigitalOVIOPD0Interrupt request to host for WLAN
30HOST_IRQ_BLEDigitalOVIOPDPDReserved for future use
31DIG_LDO_OUTAnalogODigital LDO output to decoupling capacitor
32VDD_MAIN_INPOW1.8V supply input for SRAM and digital
33nRESETDigitalIVIOPDPDReset line for enabling or disabling device (active low)
34SLOW_CLK_INDigitalIVIOPDPD32.768kHz RTC clock input
35VPP_INPOW1.8V OTP programming input supply
36FAST_CLK_REQDigitalOVIOPDPDFast clock request from the device
37GNDGNDGND
38RF_ARFWLAN 5GHz RF port
39

PA_LDO_IN

POW3.3V supply for PA
40PA_LDO_INPOW3.3V supply for PA
(1) All digital I/Os (with the exception of SDIO signals) are Hi-Z when the device is in Shutdown mode with internal PU/PD according to the "SHUTDOWN STATE" column.
(2) See software release notes for the support level.
(3) LOGGER and HOST_IRQ_WL pins are sensed by the device during boot, see CC33xx Hardware Integration.