The DAC38RFxx incorporates an optional power amplifier protection (PAP) block to monitor when the input signal is two large, for example when an interface error occurs, and reduces the output signal power of the DAC. The PAP block achieves the functionality of reducing the input signal that crosses the threshold through three main sub-blocks. These are PAP trigger generation block, PAP gain state machine and GAIN block.
The PAP block keeps track of the input signal power by maintaining a sliding window accumulation of last N samples. N is selectable to be 32, 64 or 128 based on the setting (Table 43) of fields PAPAB_SEL_DLY in register PAP_CFG_AB (8.5.35) and PAPCD_SEL_DLY in register PAP_CFG_CD (8.5.36). The average amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line (N). The result is then compared against the threshold in fields PAPAB_THRESH in register PAP_CFG_AB (8.5.35) and PAPCD_THRESH in register PAP_CFG_CD (8.5.36). If the threshold is violated, gain state machine is triggered which generated gain value to ramp down the DAC output signal amplitude. After the input signal returns to normal value, the state machine ramps up the DAC output signal amplitude.
|pap_sel_dly[1:0]||# of samples averaged|
The generation of the PAP trigger as explained as follows:
The PAP gain state machine generates the pap gain value to be applied on the output stream to reduce the output signal amplitude. The state machine below is used to control the attenuation of the DAC output and the gaining up of the signal again once the trigger is released.
The normal operating condition for the PAP block is the NORMAL state in Figure 44. However, when the PAP block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL operation to the ATTENUATE state.
In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (8.5.31) and PAPCD_GAIN_STEP in register PAP_GAIN_CD (8.5.33). This value is always positive with the decimal place located between the MSB and MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.
After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (8.5.32) and PAPCD_WAIT in register PAP_WAIT_CD (8.5.34) are used to select the number of clock cycles (samples = 16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.