SLASEA6D February 2017 – June 2020 DAC38RF82 , DAC38RF89
|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|15:14||SYSR_PHASE_WDW||R/W||00||sysref phase alignment tolerance window Centers sysref capture window as follows:
00 = Centered on phase φ12 (**DEFAULT**)
01 = Centered on phase φ23
10 = Centered on phase φ34
11 = Centered on phase φ41
|13:12||SYSR_ALIGN_DLY||R/W||01||sysref alignment offset delay Optional alignment offset that allows system designer to work around hardware (e.g. PCB) alignment errors by letting him specify that the sysref pulse should be treated as occurring one device clock earlier or later than its observed position. Legal settings are as follows:
00 = Offset by -1 device clock cycles. Treat sysref as if it were captured 1 cycle earlier.
01 = No offset (**DEFAULT**)
10 = Offset by +1 device clock cycles. Treat sysref as if it were captured 1 cycle later.
11 = Reserved
|11||SYSR_STATUS_ENA||R/W||0||Enable alignment status monitoring Enable logic that generates sysref alignment status information and accumulates statistics that can be read by the user.
0 = Disable sysref alignment status outputs (**DEFAULT**). Used during normal operation.
1 = Enable sysref alignment status outputs. Used when characterizing sysref capture timing.
|1||SYSR_ALIGN_SYNC||R/W||0||Write a ‘1’ to this bit to clear accumulated sysref align statistics|
|0||SYSR_BYPS_ALIGN||R/W||0||Bypass sysref alignment logic. Bypass the 4x oversampled sysref alignment logic and instead capture the sysref signal using the legacy implementation of a flip-flop clocked directly by the rising edge of the device clock.
0 = Capture sysref using full-featured alignment circuit (**DEFAULT**)
1 = Bypass sysref alignment logic
NOTE: When mem_sysref_bypass_align is enabled, the other sysref alignment controls have no effect.